From Glue Logic to Subsystem: Altera's Second Decade

Ron Wilson, Editor-in-Chief, Altera Corporation

The year was 1994. The U.S. Space Shuttle fleet was in regular service. The world watched in fascination as comet Shoemaker-Levy 9 broke up and crashed into Jupiter’s atmosphere. The Channel Tunnel realized a centuries-old dream, connecting England and France. Achieving the undreamt-of, the Provisional Republican Army ceased military hostilities in Northern Ireland. In the electronics industry, Intel’s recently-announced Pentium processor overcame the interruption of the famous Pentium Bug and dominated personal computing. And Altera began its second decade.

From beginnings as simple logic chips, Programmable Logic Devices (PLDs) had in ten years ridden Moore’s Law to far greater complexity—logic capacities exceeding the equivalent of 10K gate-array gates. Along the way, PLDs had divided into two architectural camps: Complex PLDs (CPLDs) based on the Boolean sum-of-products and programmed via EEPROM cells, and FPGAs, based on look-up tables (LUTs) implemented as tiny SRAMs.

The two architectures had begun to specialize. CPLDs (Figure 1) were preferred for circuits that had high fan-in or rigorous timing constraints. FPGAs favored designs that were rich in registers. A less reliable generalization held that CPLDs were more friendly to designers who thought in terms of combinatorial blocks and state machines—by 1994, the old school. FPGAs favored the younger wave of designers who visualized logic as text: Verilog or VHDL.

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