Link synchronization and alignment in JESD204B: Understanding control characters
Jonathan Harris, Analog Devices
EETimes (6/19/2013 5:43 PM EDT)
Introduction
The transition to JESD204B as the digital interface of choice for high speed data converters is well underway. The JESD204 interface was released in its original form, JESD204, in 2006 revised to JESD204A in 2008, and in August 20011 revised once more to the current JESD204B. The interface brings efficiency and offers several advantages over preceding technologies like LVDS. Designs employing JESD204B enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. There is a reduction in package pin count which leads to smaller packages and less trace routes. The standard applies to both analog-to-digital converters (A/D) as well as digital-to-analog converters (D/A), and is primarily intended as a common interface to field programmable gate arrays (FPGAs) – for example the Xilinx Kintex or Vertex platforms – but it may also be used with ASICs.
JESD204B differs from its predecessors in up-front complexity due to the new terms and parameters that it introduces. In this article, we'll take a closer examination of the control characters that are used in the JESD204 interface. Understanding the control characters helps provide a better understanding of how a link is synchronized and aligned. This helps designers to understand how to debug link issues that may arise when prototyping a design with the JESD204 interface. Each of the control characters performs a different function and helps maintain the alignment of data on the link as well as synchronization and error monitoring. If an expected character is missed or an unexpected character is received, the receiver knows that an error exists.
How it works is that the JESD204B words get mapped into valid 8b/10b encoded words and are set up in frames and multiframes with specific rules. In the process, the 8b/10b encoding provides some benefits for the serial data link by using control characters that provide the ability to perform various lane alignment functions. There are five main control characters utilized in the 8b/10b encoding that allow for various functions in the JESD204B data stream. These characters are /K/, /F/, /A/, /R/, and /Q/ control characters.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Layout Database File Control: The Missing Link
- Understanding layers in the JESD204B specification: A high speed ADC perspective, Part 2
- Understanding layers in the JESD204B specification: A high speed ADC perspective, Part 1
- Understanding the contenders for the Flash memory crown
- How control electronics can help scale quantum computers
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)