English
The Third Decade: The FPGA as SoC
Ron Wilson, Altera Corporation
In 2003, amidst the recessionary hangover from the dot-com crash, Altera began its third decade. It was a year of endings: the tragic loss of the space shuttle Columbia, the last contact with the spacecraft Pioneer 10, the last VW Beetle from the assembly line. And it was a year of beginnings: the Iraq War, the start of the great bull market in U.S. stocks, the first trans-sonic flight of the privately-developed SpaceShipOne, the first manned spaceflight by China.
In the world of system design, the elements had quietly aligned for the next stage in the evolution of FPGAs. Use of the most aggressive CMOS technology had given FPGAs the logic density and speed to implement a CPU core and its peripherals in a single chip. Altera had released Nios, a RISC CPU core optimized for FPGAs, and partners had developed FPGA implementations of other popular CPU cores as well. Avalon, a multi-master bus architecture tuned for use in programmable logic, normalized interconnects between CPUs and subsystems on the chip. And a tool to add automation to the process of assembling intellectual property (IP) into an FPGA-based SoC, SoPC Builder, reached the market.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Intel FPGA Hot IP
Related Articles
- eFPGA LUTs Will Outship FPGA LUTs Later This Decade
- Setting up secure VPN connections with cryptography offloaded to your Altera SoC FPGA
- Tackling large-scale SoC and FPGA prototyping debug challenges
- Addressing the new challenges of ASIC/SoC prototyping with FPGAs
- Cost-effective SoCs are the key to fostering innovation
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)