Verification challenges of ADC subsystem integration within an SoC

Snehal Rathi, Shubhra Singh, Garima Jain (Freescale)
EDN (September 30, 2013)

The real world is analog in nature. Any information which needs to be captured from our surroundings is always an analog value. But processing of analog data in a microprocessor requires that the data be converted to its digital equivalent first. For this, different kinds of ADCs (Analog to Digital Converters) are used in an SoC. Depending on a few parameters, namely the throughput, the immunity to noise, and the complexity of design, the type of the ADC is chosen.

An SoC designer is not required to know the deep design intricacies of any IP they are integrating into the SoC. So even from the perspective of an SoC designer, if the ADC is considered as a black box, there are many factors that decide the quality of performance of the ADC at the SoC level. We must take care of these factors.

The conversion of an analog signal into digital data requires discretization in both time as well as amplitude. The discretization in time happens in the sampling phase and the discretization in amplitude happens in the quantization phase. Sampling is done using a sample hold circuit. A sample hold circuit has a switch, a resistive path and a capacitance on which the voltage is sampled when this switch is closed. The quantization in very simple terms is the scaling of the sampled value to a digital value within a range (governed by the reference voltage of the ADC).

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