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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Dealing with SoC metastability problems due to Reset Domain Crossing
Arjun Pal Chowdhury , Neha Agarwal and Ankush Sethi, Freescale Semiconductor India Pvt LTD
embedded.com (November 10, 2013)
Metastability in design due to asynchronous clock domain crossing (CDC) is a well known problem. Industry standard advanced tools are available to catch such structural or functional issues in design.
However, CDC is not the only reason a signal becomes asynchronous with respect to the destination clock domain. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will create an asynchronous crossing path and cause metastability at destination register. Referred to as Reset Domain Crossing (RDC), it occurs when the reset signals of launch and capture flops are different.
This article will review some of the conditions under which RDC occurs and propose some ways to deal with the problems that occur up front in the design phase.
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