Using USB 3.1's Multiple INs To Reach 10 Gbps Data Rates
Matthew Myers, Synopsys
Semiconductor Engineering (January 16th, 2014)
When working with USB 3.1, designers are challenged to provide the 10 Gbps USB 3.1 speeds that customers expect while supporting backward compatibility with USB 3.0 devices in a hub topology.Using multiple INs provides a greater level of flexibility to the system.
In January 2013, the USB-IF announced USB 3.1, a new generation of the protocol that will double USB 3.0 data throughput performance to 10 Gbps. In addition to this increased speed, the specification requires compatibility with existing cables, connectors, software stacks, and device class protocols. USB 3.1 products must support existing 5 Gbps and new 10 Gbps hubs and devices, as well as older USB 2.0 products. To meet this long list of requirements, more needs to be done than simply increasing the physical layer data rate from 5 Gbps to 10 Gbps. In addition to the PHY changes, designers must implement carefully thought-out protocol changes, such as the use of multiple INs, to take advantage of the additional bandwidth.
Complexities of USB 2.0, 3.0, and 3.1 speeds through a hub
One of the reasons USB is so popular is because it is based on a hub topology that allows the expansion of connections. Even if a PC only has one USB port, it is theoretically possible, through multiple levels of hubs, to connect to more than 100 devices. However, the presence of hubs in the system and the requirement for backward compatibility with slower devices combine to make the protocol much more complicated when trying to increase the data rate.
E-mail This Article | Printer-Friendly Page |
|
Synopsys, Inc. Hot IP
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- System Verilog Assertions Simplified
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
- Dynamic Memory Allocation and Fragmentation in C and C++
- Synthesis Methodology & Netlist Qualification