Ceva-Waves Bluetooth 5.3 Low Energy Baseband Controller, software and profiles
Analog IP business not likely soon, say DAC panelists
Analog IP business not likely soon, say DAC panelists
By Richard Goering, EE Times
June 13, 2002 (1:34 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020612S0054
NEW ORLEANS - A commercial analog intellectual property (IP) business is not likely to emerge any time soon, judging from comments on a Tuesday (June 11) panel at the Design Automation Conference here. While the panel represented a range of views, there was little optimism for anything beyond hard IP blocks that are silicon-proven for a given foundry. Among the more skeptical panelists was Roy McGuffin, president and CEO of Antrim. To be successful, he noted, commercial IP has to be reusable and retargetable. "Typically that's been achieved for digital, but in analog, it's a goal that's never been achieved," he said. McGuffin said that "commodity" analog IP will default to proven silicon from a foundry, and that "custom" IP, which represents more complex analog functions, will remain an in-house competency. And in both cases, he said, it will be hard IP. "We don't believe there is a sustainable market for commodity soft analog IP," he said. Even more gloomy was Masao Hotta, senior chief engineer for semiconductor and integrated circuits at Hitachi. "Analog blocks can be reused only within the same process and the same application," he said. "It will be very difficult for analog IP to reach the same success as digital." Hotta noted that digital blocks have only two parameters - delay and fanout - while analog blocks have a "huge number." That list includes bandwidth, accuracy, slew rate, noise, offset, signal swing, among others. Further, said Hotta, analog blocks are "sensitive to everything," including layout, proximity, and noise from ground and power supplies. "The thing often overlooked is that if things go wrong, if there's a problem with the analog IP, who takes responsibility?" he asked. Rudolf Koch, head of the RF design group at Infineon Technologies, said that his group has never purchased any external IP. He outlined the obstacles to the use of analog IP - the need for extensive rework in RF design, the complexity of veri fication, missing standards, and no clear responsibility if problems arise. He also noted that the costs of buying IP are visible, but the cost savings for it are not. Mike Brunolli, CTO of IP provider Nurlogic Design, had a contrary view. "We believe analog IP is becoming a growth business," he said. He noted, however, that the way it's productized, delivered, and supported is crucial. If analog IP is at too low a level - op amps, for instance - the IP provider ends up becoming a "consultancy," Brunolli said. "You can mitigate this by providing a higher level of functionality," he claimed. Long-range optimism came from Ted Vucurevich, chief architect and fellow at Cadence Design Systems. He said that a shift in silicon economics is resulting in a need for aggregation, in which tens of thousands of analog IP blocks could potentially be put on a 300 mm wafer. This, he said, will cause more people to think about reuse. Vucurevich also pointed to research in analog modeling and optimization tha t could make analog IP more practical. He said the question of analog IP is "not a digital yes or no, but a continuous function. I believe that over the long term we'll progress from very few people using it to a lot more people using it." Andrew Moore, design service marketing manager at TSMC North America, said that analog IP is in active use now - and to prove it, he displayed a list of TSMC's analog IP portfolio, including PHY, LVDS, USB 2.0, and Bluetooth blocks as well as PLLs, ADCs, and DACs. All are hard blocks that have been silicon-proven. What's crucial to the success of analog IP, he said, is prototyping. In response to a statement from an audience member, panelists scoffed at the notion of "silicon-proven" soft analog IP. McGuffin called it an "oxymoron." Brunolli asked how a compiler that can generate thousands of implementations can be silicon proven. "Synthesizable or not, if you take a piece of analog IP and cram stuff around it, proximity effects and substrate effects can kill y ou," said Moore. "You need prototyping." Moore expressed hope that another vendor will enter the substrate noise market, now that Cadence has pretty much wrapped it up by buying Simplex.
Related Articles
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- Optimizing Analog Layouts: Techniques for Effective Layout Matching
- Key considerations and challenges when choosing LDOs
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- Simplifying analog and mixed-signal design integration
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Demystifying MIPI C-PHY / DPHY Subsystem
E-mail This Article | Printer-Friendly Page |