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The hardware (and software) implications of endianness
Sandeep Yaddula, Texas Instruments
embedded.com (March 02, 2014)
Embedded software programmers are familiar with the endianness characteristic of a computing processor, insofar as it refers to how bytes of a data word are ordered within memory.
Taking their name from Jonathan Swift's book Gulliver's Travels, big-endian systems are systems in which the most significant byte of the word is stored in the smallest address given and the least significant byte is stored in the largest. In contrast, little endian systems are those in which the least significant byte is stored in the smallest address.
So, depending on endianness, data types are stored differently in memory, which means there are considerations when accessing individual byte locations of a multi-byte data element in memory. In this article, we will review the concept of endianness from a software standpoint and then look at the implications of endianness for hardware IP block designers and device driver developers when they work with a complex system such as a modern System-on-Chip (SoC).
Today’s SoCs integrate many hardware IP blocks; designers need to be aware of the order of bytes on the byte lanes of connecting buses when transferring data. In a system with several discrete hardware components - such as a host processor and external devices connected to it via a PCI bus, for example - the hardware components may support different endianness modes. Device driver developers need to make the data transfers among these hardware components endianness-proof.
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