Auto Clock Generation in a SoC

Mrugesh Walimbe, Mahesh Penugonda (Open-Silicon)

Abstract:

This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting language is used to parse the input file. The script generates Synthesizable System Verilog RTL, System Verilog Assertions, Clock Constraints and Documentation in HTML format.

As the complexity of a SoC is growing in terms of functionality and there are many requirements to generate different clock frequencies and associated clock requirements. At the same time the average SoC development schedule has shrunk. The SoC design challenges that are addressed in this paper include scalable clock design methodology, reduced human efforts/error, adherence to standard design practices, soft errors, low power controllability, reduced turnaround time for clock specification changes, enabling physical design process, documentation aspects and reduced verification efforts.

This automation of Clock Generation results in quick implementation of clock requirements in a SoC.

Introduction

With the increase in size and functionalities of a SoC, any architectural changes lead to more time to design and implementation. A typical SoC today has a complex clock structure derived from multiple sources that enable its function. Any design changes related to clocks in a SoC results in more time to implement and are bug prone.

This paper describes an algorithm for automating clocks generation RTL in a SoC. This algorithm has faster implementation and reduces turnaround time for architectural changes related to clocks.

The algorithm requires a pre-defined input. Once all the required data are entered by the designer, the algorithm script parses the input and generates clock gen RTL files, clock constraints, assertions for verification and documentation.

The current implementation of algorithm has considered Microsoft Excel sheet as input file, perl as scripting language, SystemVerilog as HDL and HTML as documentation format.

However, this algorithm implementation doesn’t restrict designers to adopt above mentioned formats.

Clocks Generation in a SoC

In a SoC, one of the sources for generating the internal clocks is PLL. PLL output clock is used as source clock by clock generation block. Divisor circuits and necessary glue logic are used to generate the required clocks. Below diagram shows the clock generation circuitry in a SoC.

In the below diagram, ref_clk can be generated externally (for ex: crystal clock). It is used to drive PLL input clock. Upon configuring the PLL to the required frequency, it generates “pll_clk” output. The clock gen block has internal logic to generate multiple clocks as per requirement. The clock outputs may or may not share attributes such as phase, clock mux, clock gates etc.

Algorithm Details

Based on the input frequencies to be derived from source clock, statistical analysis is done and four categories of clocks are formed. From the formed categories, sort groups are extracted from these categories to generate clocks in phase with the source clock, glitch free and low gate count. This statistical information of sort groups from the generated sheet is parsed to generate RTL, SDC and HTML documentation.

Algorithm has multiple sequences to execute and derive clock gen RTL, assertions, clock constraints and HTML document.
Designer has to enter the values of various fields mentioned in predefined format of the input sheet.

Fields of type reference clock frequency, reference reset, names and frequencies of those clocks to be derived, requirements like clock mux, clock gating etc.

Upon entering the fields as required, scripting language is used for parsing the input sheet and designer enters the required command to generate the following:

• User has the necessary option to pass to scripting language in order to insert assertions in the RTL.
• User has the necessary option to pass to scripting language in order to generate clock constraints.
• Scripting language generates document in the form of HTML format describing the reference clock, generated clocks and its frequencies.

Figure 2: Algorithm Flow



Figure 3: Algorithm Execution

Sample Implementation

Input sheet format under consideration is Microsoft Excel and there are various fields mentioned in blue to be entered by designer and red fields indicate auto calculated fields. Designer has to press “Generate_sort_groups” and the result excel sheet is used for parsing by scripting language.

There are other fields/labels like “start_row”, “divisor_col” in black which needs to be entered by the designer.

Figure 4: Sample Input Sheet.

A. Sample Generated RTL

module clk_gen (
clk_400,SOURCE_CLK,resetn,clk_200);
//-------------List of Inputs-------------//
input SOURCE_CLK, resetn;
//---------------List of Outputs--------------
output clk_400, clk_200;
//---------------Internal wire declarations---------
wire clk_400;
//--------------- Internal logic declarations -------------
logic clk_200;
//---------------------- Internal assignements ------------
assign clk_400 = SOURCE_CLK;
//--------------- Internal clock generation logic --------

always @(posedge SOURCE_CLK or negedge resetn)
begin
if(!resetn) begin
clk_200 <= 1'b0;
end
else begin
clk_200 <= ~clk_200;
end
end
endmodule

B. Sample Generated Constraints

create_clock -name SOURCE_CLK -period 2.5 - waveform {0 1.25} [get_ports SOURCE_CLK]

create_generated_clock -name clk_400 -source [get_ports SOURCE_CLK] -divide_by 1 [get_ports clk_400]

create_generated_clock -name clk_200 -source [get_ports SOURCE_CLK] -divide_by 2 [get_pins counter_SOURCE_CLK_2]

C. Sample Generated HTML file.

Figure 5: Sample generated HTML File

D. Sample Generated Assertions

`ifdef DESIGN_ASSERTIONS_ON
`define
ASSERT_CLOCK(a_name,clk_in,clk_en,clk_out)
a_name:assert
property(assert_clock(clk_in,clk_en,clk_out));
property assert_clock(clk_in,clk_en,clk_out);
@(posedge clk_in)
(clk_en == 1) |-> (clk_out == 0);
endproperty
`ASSERT_CLOCK(a_clk_120,cm_clk_120,dsync_en_120,cg_clk_120)
`endif

Generated Output Files

Generated system Verilog RTL files that are generated on executing the algorithm are:

clk_gen.sv,
clk_mux.sv,
clk_mux_4.sv,
cg.sv,
flop2_sync_param.sv,
flop2_sync.sv.

Apart from the above RTL files, below are other outputs that the algorithm generates:

1) Clkgen.sdc -> Clock constraints file

2) Clkgen.html -> Documentation