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The "BIST" Thing That Happened to SoC Design
by Philip George and James Fujimoto
Not so long ago, in a design galaxy that now seems far, far away, RTL designers did not have to worry about a testable integrated circuit (IC). "Leave that to the test guys," they would say, and it was so.
However, as chip complexity increased and designers turned to complex system-on-chip (SoC) designs, test was taking more and more time and test engineers were complaining that the designers were creating virtually untestable designs. Test costs were going out of control as the cost of test was rivaling the cost of manufacturing a chip.
"There has to be a better way," the test engineers complained. And sure enough, there was a better way, with embedded test. By designing testability into the chip design in the first place, RTL designers can significantly reduce the cost of test.
Not so long ago, in a design galaxy that now seems far, far away, RTL designers did not have to worry about a testable integrated circuit (IC). "Leave that to the test guys," they would say, and it was so.
However, as chip complexity increased and designers turned to complex system-on-chip (SoC) designs, test was taking more and more time and test engineers were complaining that the designers were creating virtually untestable designs. Test costs were going out of control as the cost of test was rivaling the cost of manufacturing a chip.
"There has to be a better way," the test engineers complained. And sure enough, there was a better way, with embedded test. By designing testability into the chip design in the first place, RTL designers can significantly reduce the cost of test.
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