English
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Multi-faceted design verification
Robert Eccles, Calypto Design Systems
EDN (August 04, 2014)
Design verification is increasingly complex. Designers spend more than 50% of the overall design schedule in verification. Verifying functionality involves multiple tools and multiple views of the circuit, with functional simulation as the primary method. The design is subjected to a number of test vectors, and the results are compared against an expected result. The process is slow and is only as good as the vectors used.
Designers have also relied on other methods for design verification that provide alternative views that give added insight into a design. Lint checkers provide a different viewpoint from simulation by through static analysis of the RTL code. They report suspicious RTL constructs and style differences, and the ensuing reports are studied to identify potential issues with the circuit. Static timing analysis (STA) finds long timing paths. STA may show that there are more levels of logic in one path than expected, indicating either a design or a synthesis issue. For example, unwanted priority encoding could add more levels of logic than expected. Simple code coverage metrics verify design functionality. Code coverage tools can find code that is not exercised in simulation. This code is either useless or untested.
A new technique has emerged that uses power analysis to verify design functionality. In this approach, designers put together vectors for the maximum power conditions. This can trigger modes of operation that uncover functional issues not covered by normal simulation or any other techniques. This is particularly useful if the RTL power analysis can be done with sufficient accuracy.
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