English
SoC tool flow techniques for detecting reset domain crossing problems
Arjun Pal Chowdhury, Neha Agarwal, and Ankush Sethi, Freescale India
embedded.com (August 13, 2014)
In a sequential system on chip designs, if the reset of source register is different from the reset of destination register, even though the data path is in same clock domain, this can cause an asynchronous crossing path to occur which can cause metastability at destination register [1].
This paper proposes a verification tool flow which can be used with any SoC structural verification tool to detect such reset domain crossing (RDC) problems. It also describes some techniques to make the SoC design tools you use intelligent enough to weed out false violations.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Dealing with SoC metastability problems due to Reset Domain Crossing
- SoC Verification Flow and Methodologies
- Four ways to build a CAD flow: In-house design to custom-EDA tool
- SoC Functional verification flow
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
New Articles
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Congestion & Timing Optimization Techniques at 7nm Design
- Optimizing Analog Layouts: Techniques for Effective Layout Matching