SoC tool flow techniques for detecting reset domain crossing problems
Arjun Pal Chowdhury, Neha Agarwal, and Ankush Sethi, Freescale India
embedded.com (August 13, 2014)
In a sequential system on chip designs, if the reset of source register is different from the reset of destination register, even though the data path is in same clock domain, this can cause an asynchronous crossing path to occur which can cause metastability at destination register [1].
This paper proposes a verification tool flow which can be used with any SoC structural verification tool to detect such reset domain crossing (RDC) problems. It also describes some techniques to make the SoC design tools you use intelligent enough to weed out false violations.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Dealing with SoC metastability problems due to Reset Domain Crossing
- SoC Verification Flow and Methodologies
- Four ways to build a CAD flow: In-house design to custom-EDA tool
- SoC Functional verification flow
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
New Articles
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics