Pinning down the acceptable level of jitter for your embedded design

Dean Smith, Integrated Device Technology
embedded.com (August 26, 2014)

There are several clock jitter types, measurement methodologies, and corresponding specifications. But most hardware designers don’t have the time to research these, and the detailed nuances of clock jitter specifications can seem like trivial minutia to the board designer.

The designer is often more focused on the larger design task(s) at hand. Taking precedence are design tasks specific to FPGA logic, microprocessor complex, data plane switch fabric, control plane switch fabric, RF signal chain, power, interconnectivity issues, design simulation, modeling, etc.

So, the designer must assume that the reference clock jitter specifications from the various chip vendors are relevant for their intended use of these devices, and that they are also specified completely and correctly.

But without some basic guidelines to follow, the designer could over-specify the clock jitter requirements and add undue bill of material (BOM) cost to the design with more expensive clocks devices. Or, even worse, the clock jitter requirements could be under-specified and corresponding errors will increase beyond an acceptable error rate for the given application. This may not be determined until after performance metric testing of initial prototype boards very late in the development cycle, potentially impacting end product release schedules.

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