Product how-to: Reliable SoC bus architecture improves performance

Deepak Shankar & Ranjith K R
EDN (September 23, 2014)

This paper describes a modeling project to architect the bus topology and evaluate the read/write traffic patterns for a new multimedia System-On-Chip. Using the selected modeling and simulation exercise, we were able to validate the entire architecture in three months. In the process, we learned about architecture behavior and were able to test a large number of operating scenarios to achieve optimum performance in minimal time.

We have developed the system level model of a multimedia SoC with three different bus architectures using a combination of Advanced Microcontroller Bus Architecture (AMBA) Advanced High-performance Bus (AHB) and AMBA Advanced Peripheral Bus (APB). We have found that systems with both AMBA APB and AHB have proven to be more advantageous with respect to performance and power when there is a constant change in the traffic rate of peripheral devices as opposed to systems with only AMBA AHB or AMBA APB. The pre-built libraries and extensive reports provided an edge to this modeling and simulation approach over other approaches by saving us a substantial amount of time. Also, it raised our level of confidence in the quality of the final SoC including the read/write latency and processing throughput.

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