Bridging the gap between speed and power in Asynchronous SRAMs

Anirban Sengupta and Reuben George, Cypress
EDN (January 05, 2015)

The Asynchronous SRAM space is divided between two very distinct product families – fast and low power – each with its own set of features, applications, and price. Fast Asynchronous SRAMs have faster access time, but consume more power. Low-power SRAMs save on power consumption, but have slower access time.

From a technological standpoint such a trade-off is justifiable. In low-power SRAMs, special Gate-induced Drain Leakage (GIDL) control techniques are employed to control stand-by current and thus standby power consumption. These techniques involve adding extra transistors in the pull-up or pull-down path, as a result of which access delay increases hence increasing access time. In Fast SRAMs, access time is the highest priority and hence such techniques cannot be used. Moreover, the transistors are scaled up in size to increase charge flow. This scaling-up reduces propagation delay but at the same time increases power consumption.

From the standpoint of application requirements, this trade-off has led to two distinct application bases. Fast SRAMs work well as a direct interface cache or scratchpad expansion memory for high-speed processors. Low-Power Asynchronous SRAMs are used to temporarily store data in systems where power consumption needs to be very low. Hence, while Fast SRAMs are typically used in high performance systems like servers and aeronautical devices, Low-Power SRAMs are used most in battery-powered devices like POS terminals and PLCs.
However, technological advancement is driving more wired devices to battery-backed mobile versions. For the past few years, we have also been witnessing the introduction of a plethora of wireless applications leading to a wireless gadget boom. This new generation of medical devices, handheld devices, consumer electronics products, communication systems and industrial controllers, all driven by the Internet of Things (IoT), is revolutionizing the way devices function and communicate. In such mobile devices, both Fast and Low-power SRAMs fail to service the need comprehensively. Fast SRAMs have high current consumption and thus drain the battery too quickly. Low-power SRAMs are not fast enough to handle the demands of such complex devices.

For all key components of modern electronic devices, reducing power consumption and footprint are two of the biggest challenges at hand. For Asynchronous SRAMs, the challenge translates to creating a Fast SRAM that consumes considerably less power, all in a small footprint. While many SRAM manufacturers have started offering products in small pin-count and die-sized packages, the demand for low-power high-performance memory hasn’t been met.

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