An MLC ROM With Inserted Redundancy and Novel Sensing Scheme

Star Sung, Blue Lan, Jacques Baudier (Taiwan Imaging Tek Corporation (TITC))

Abstract :

An Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 16M bits (actual 32M bits) density is presented. The MLC ROM is designed by a 0.090 μm CMOS logic process. The ROM cell of 0.40μm ×0.50μm with 0.03μm per step of the channel width and channel length increase is determined to obtain 4 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 5 ns. 4 bits per cell can be achieved by inserting more referencing columns of ROM cells to track and to compensate noise from power and ground bouncing.

1. INTRODUCTION

A semiconductor memory is typically comprised of an array of memory cells which are aligned in rows and column. A memory cell is used to store data for future use. For area efficiency, a memory array includes a large amount of memory cells. A word line, WL runs across top of hundreds or even thousands of memory cell gates which makes the WL capacitance load quite large and needs a big driver to accelerating the speed of charging up the capacitive load of memory cells hooked to the same word line charging and discharging the large display panel capacitance.

The Read Only Memory, ROM has advantages of small cell size and fully compatible standard CMOS logic process and therefore costs least price to manufacture compared to its counter parts other memories like SRAM, DRAM or some Non-Volatile Memories, NVM including flash or EPROM memories. A conventional ROM cell as shown in Fig. 1 is commonly comprised of an N-type device 1 with a fixed channel width and length. The gate of the ROM device is hooked to a world line while another node of diffusion, so named as “drain” is hooked into a so named “bit line” and the other node of diffusion is grounded to the return of power supply which in most likely grounded to “0V” in a standard CMOS process. In the mask design or layout of the ROM cell as shown in top right of Fig. 2 a contact is used to connect drain of diffusion node to a bit line, a poly running across top of the thin oxide layer forms the gate of an ROM cell which is connected to the word line. For reliability of cell size, there will be minimum spacing between the contact and the edge of diffusion area and the spacing between an edge of diffusion to the poly. Most ROM cell in CMOS process use a minimum channel length of NMOS device. The spacing between the contact and the edge of diffusion plus the shape of contact determines the area of an ROM cell.

Fig. 3 The innovated MLC ROM Cell Layout

2. FUNDAMENTALS OF THE INNOVATED MLC ROM CELL STRUCTURE

The conventional ROM cell has a fixed channel width and length and a fixed threshold voltage. This limits the density of representing one bit for each ROM cell. The innovated MLC (Multi-Layer-Cell) ROM has 3 selectable variable width and an option of contact to connect the diffusion to Ground (GND) or let it be floating as shown in Fig. 3. An optional 7 width and a 6 width 3 length can achieve 4 bpc. In 2 bits per cell choice, since the contact to diffusion edge has a minimum spacing causing extra space waste, and one can apply 3 widths to sink 3 current flows plus a contact not connect to GND resulting in 4 levels of current sinking strengths which can identify 2 bits.

2.1 3-4 bpc Cell Structure

To achieve even higher density like 3 pbc or even 4 bpc, 1-3 additional “Lengths are selected to obtain 8 and 18 (6 widths x 3 Lengths) (W/L) beta ratios and 8/18 current sinking strengths with very limited cell size increase of 15% to 30% reaching an efficiency of cell area per bit of increase of 25% to 50%. In 3 bits per cell structure, 8 selectable levels of width is applied to provide a cell capable of storing 3 bits or 4 levels of width combined with 2 levels of Length supplying 8 current sinking strengths. While, for efficiency, in 4 bits per cell structure, 3 levels of Length combined with 6 levels of Width with a total of potential 18 levels of current sinking strength.

2.2 Options for Higher Than 4 bpc Cell Structure

A couple of combinations of cell including:

• Multiple Threshold Voltage (MTV) with Multiple Width or/and Multiple Length.
• Multiple Diffusion Resistance (MDR) by multiple Doping Density combined with Multiple Width or/and Multiple Length.
• Intelligent sensing scheme to differentiate the current strength between each level including specialized Referencing Cell of an small array of Referencing Cells and the best Colum of cells can be selected to be the referencing cells.

Fig. 4 Sensing Scheme with Referencing Columns

Fig. 5 Sensing Margin Analysis

3. THE INNOVATED SENSING SCHEME WITH REFERENCING COLUMNS

Due to small margin among current sinking strength levels and enabling time, care must be taken to ensure the accuracy of reading out the right cell data and converted to be the correct digital information. Fig. 4 depicts the innovated sending scheme with 3 referencing columns of cells. 3 referencing cells R1, R2 and R3 in each column have variable current sinking strengths by 3 NMOS channel widths to differentiate the sinking speed of 4 potential ROM cells with variable channel width. The ROM cell with no contact to Ground will keep the Bit Line in pre-charged voltage level which is most likely in Power supply, the cell with widest channel width will pull down the Bit Line voltage quickest. Two other kinds of ROM cells with levels of in between pull down the Bit Line voltage moderate strength pulling the bit line voltage down. The timing controller turns enables the three sense amplifiers SA with 2 input each, V_R1, V_R2 and V_R3, V_BL1, V_BL2 and V_BL as shown in Fig. 5, while, the output results of 3 SAs are decoded into 2 logic stage and latched to the two bits Flip Flops for output.

3.1 Reference Columns to track and to compensate the noise from Power and/or Ground Bounce

Since MLC memory sensing margin is narrow, noise from Power supplier or Ground can easily cause error in reading out the data info within the MLC cell. Locally inserting 3 referencing columns of ROM cells with each referencing cell sharing the same Word Line (WL) and easily tracking all noise caused WL and BL fluctuation and mainly from Power noise and Ground bouncing.

3.2 Current to Voltage Conversion and ADC

To achieve higher accuracy with reasonable cost of sensing power, a two stage sending architecture is implemented as shown in Fig. 6. The current sinking in the ROM Array cell is converted into corresponding voltage level and input to the sense amplifier. The timing controller turns enables the 4 bits ADC and the output results of 2 bits MSB and latched to the two bits Flip Flops for output in the 1st timing slot, and the 2nd time slot the other converted LSB bits are latched. Since two steps are applied to convert and to store the sensed data, the accuracy gets secured.

Fig. 6: Sensing Scheme with a Current-to-Voltage Converter and a 2 steps ADC

4. INNOVATED SENSING SCHEME TO INCREASE THE YIELD

In all MLC Multiple Layer Cell memory design, no matter what type of memory device or circuit, the sending margin is relatively small compared to SLC.

Each bit increase, one half the sensing margin will be obviously seen in the amplifier and higher risk of failure. Some alternatives of sensing schemes are applied to increase the yield including:

1. Multiple Referencing Columns. As shown in Fig. 7 which in case of failure comes from narrower margin in Referencing Column.
2. Centralized small Referencing Array with larger Referencing Cells.
3. More frequent Referencing Column.

Fig. 7. Inserting more Referencing Columns or a smaller Referencing Array of ROM cells

5. VLSI IMPLEMENTATION WITH TSMC 90 NM PROCESS

An 4Kx4K, 16M bit cell an equivalent 32M bits ROM array is implemented by a TSMC 90nm CMOS process. The NMOS ROM cell is 0.40um x0.50um. To avoid process deviation and noise fluctuation, every 256 columns of ROM cells inserted a 3 columns of referencing ROM cells making the referencing column dominate 1.56% of array area.

Word Line and WL Driver dominate 3.44% width of the 16M cells’ array, The Bit Line decoder, Sense Amplifiers and output decoder and FF dominate 4.6% Array Area resulting in a total of 9.60% of overhead of the additional peripheral circuitry. The ROM array of 16M cells (32M Bits) is comprised of1,680um x 2,092um die area. Higher density can reduce the % of the peripheral circuitry from 9.6% down to 6.7%.

Fig. 8 Timing Simulation Result of 4 bpc

6. CONCLUSION

The simulation with TSMC 90nm CMOS process shows 4.6ns Tacc of 2 bpc and 10.0ns Tacc of 3 bpc and 20.0ns Tacc of 4 bpc. This Macro is ready for production. Higher yield can be achieved including:

1. Higher accuracy sensing scheme and circuitry design is needed to gain higher access speed as well as higher yield.
2. A good referencing column of cells and redundant referencing columns of cells as well as redundant column of MLC ROM.
3. More study on redundancy vs. yield increase in both redundancy of memory cell arryay as well as in reference column.
4. Multiple Threshold voltage coupled with multiple Width and Length with novel sensing scheme to achieve higher bit per cell.

ACKNOWLEDGEMENT

The authors would like to express their appreciation to R&D teams of TITC, Novatek, Orise, Himax and Renesas, Panasonic, Magnachips as well as Mr. Herve PIERROT, and Gilles Ries, a design manager at ST for their excellent and hard work on the system design and FPGA porting. Mr. Thomas Chang, an VP of VIS (a daughter firm of TSMC) has in the past years provided lots of expertise in memory design which plays a critical role of this work.

REFERENCES

[R01] Siddhant Kukreti, Gurmohan Singh, Vemu Sulochana A Low Power 32 Bit CMOS ROM Using A Novel ATD Circuit.

[R02] Donghui Wei and Ian K. Craig Economic performance assessmentof two ROM ore milling circuit controllers