Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
The future of custom ASICs
Donnacha O’Riordan, S3 Group
EEtimes Europe (February 26, 2015)
For decades, electronics product innovation has been incremental in nature, relying largely on the next generation of semiconductors to deliver performance improvement. For almost 50 years Moore’s Law has delivered 2x performance (power or cost) improvement in semiconductors every 18 months, outpacing any product or system level innovation cycle that could be achieved by even the most ambitious hardware teams. What has evolved is a “sit & wait” approach, to product innovation. However it is now clear that Moore’s law is broken, and the implications are profound for hardware designers.
The Semiconductor industry is consolidating, into fewer huge players. The fabless model is under increasing strain favouring only the most massively distributed companies. Hardware product teams can no longer “sit & wait” for performance improvement to be delivered by semiconductor companies, architecture is becoming more relevant, it becomes feasible – even necessary, for product teams to develop their own custom ASICs.
Here, I highlight some of the trends that have caused the hardware industry to favour a “sit & wait” approach to innovation, and looking forward 5 to 10 years, suggest what will be a fundamental shift in how hardware product innovation happens.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware