Memory fault models and testing
Abhilash Kaushal, Freescale
EDN (June 29, 2015)
A different set of fault models and testing techniques is required for memory blocks vs. logic. MBIST algorithms that are used to detect faults inside memory are based upon these fault models. This article discusses different types of memory fault models.
Memory fault models – Single cell faults
Stuck at (SAFs): Stuck at faults in memory is the one in which the logic value of a cell (or line in the sense amplifier or driver) is always 0 or 1.
Left: Write operation state diagram of a good memory cell; Right: State diagram for s-a-0 and s-a-1 memory cell
Transition Faults (TFs): In transition faults a cell fails to make a (0 to 1) transition or a (1 to 0) transition when it is written; up transition fault is denoted as <0w1/0/- > and a down transition fault is denoted as < 1w0/1/- >
State diagram for transition faults
Write destructive faults (WDFs): A non transition write operation in a memory cell causes the cell to flip. There are two types of Write destructive faults:
1) Memory cell in state 0, write 0 on it. Cell becomes 1. Denoted as <0w0/1/->
2) Memory cell in state 1, write 1 on it. Cell becomes 0.Denoted as <1w1/0/->
State diagram for write destructive faults
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Memory Testing - An Insight into Algorithms and Self Repair Mechanism
- Accurate memory models for all
- Verifying embedded software functionality: fault localization, metrics and directed testing
- Better memory models support SoC verification tasks
- SoC Test and Verification -> Leveraging memory for better fault tolerance
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)