DDR simulation strategy catches bugs early

Ankit Khandelwal & Neha Srivastava (Freescale Semiconductor)
EDN (July 16, 2015)

DDR verification is one of the most critical and complex tasks in any SoC as it involves a controller sitting inside the DUT and an external DDR memory sitting outside the DUT on board. A DDR system consists of a controller, I/O, package, socket, power supply, clock, and an external memory all working together. In digital verification, not all of these components come into the picture, but primarily the controller, PHY, I/O, and memory. Verification becomes even more complicated as the effects of all the components is impossible to imitate in digital simulations, but Gate Level Simulation (GLS) gives us a good infrastructure to report the design issues that can plague the controller-PHY-I/O path mainly from a timing perspective.

A lot of issues related to timing are encountered while verifying DDR in GLS which leads to a lot of iterations between the verification and STA (Static Timing Analysis) teams. Having a clean debugged GLS environment gives confidence in the STA perspective of the DDR protocol over the RTL (Register Transfer level) runs and can give a good confidence focused on the digital and timing aspects. This paper collates a broad level of issues generally reported in GLS (Gate Level Simulation) verification for DDR due to timing visibility over RTL and highlights important debug criterion for quick and efficient closure of DDR on GLS environment through a number of examples.

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