Agile Design for Hardware, Part I
David Patterson and Borivoje Nikolic, UC Berkeley
7/27/2015 07:00 AM EDT
In the first of a three-part series, two Berkeley professors suggest its time to apply Agile design techniques to hardware.
Software used to be developed as a sequence of distinct phases, each of which can take six or more months:
- Requirements analysis and specification
- Architectural design
- Implementation and integration
- Verification and test
- Operation and maintenance
This process is the called the Waterfall development model, since it flows from the top down to completion. Waterfall relies on extensive documentation, planning, and using PERT and Gantt charts to try to make the schedule match the budget.
So many software projects were late, over budget, or abandoned that it led to a revolution in software development, demarcated by the Agile Manifesto in 2001. Agile development embraces change as a fact of life; small teams continuously refine a working but incomplete prototype until the customer is happy with the result. What to do in the next iteration depends on the evaluation of the current one, as opposed to some master plan established at the beginning of the project. Thus, the elaborate planning and documentation of the Waterfall process is moot.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- Agile Design for Hardware, Part II
- Next Gen Scan Compression Technique to overcome Test challenges at Lower Technology Nodes (Part - I)
- Is Agile coming to Hardware Development?
- Dealing with automotive software complexity with virtual prototyping - Part 2: An AUTOSAR use case
- Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow