English
Giga-Scale Challenges Plague Memory Design
Zhihong Liu, CEO, ProPlus Design Solutions
EETimes (8/27/2015 00:01 AM EDT)
Advanced designs are more complex and larger than ever before and designers are balancing between accuracy and performance for large scale memory simulation and verification, fine-tuning options and settings for each circuit type
Advanced memory designers always use cutting-edge fabrication technologies for larger integration density and faster operating speed, while conserving low-power consumption. After all, memory chips are critical components that determine system performance and power.
Similarly, embedded memory IP is also the critical piece of the SoC puzzle, consuming more than 50% of the die area of a chip. No matter what type of memory IP or memory IC –– DRAM, SRAM or flash –– greater design complexity is creating massive, giga-scale challenges, which are the last thing circuit designers need or want.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow