Methods to Fine-Tune Power Consumption of PCIe devices

Philippe Legros, Romain Tourneau (PLDA)

Introduction

A basic paradox of electronic evolution is the desire to enable the execution of more functions while consuming less power and silicon area. For PCIe® applications, this goal is not a new one. A PCI power management specification has been available since 1997, and PCI Express® has featured native power management since its initial release in 2002. In addition, there has always been a recognized need for low power in the mobile market.

Historically, advances in ASIC technology have led to reductions in power, but this is no longer the case for the smallest geometries due to much higher leakage power. Leakage power—the power consumed by unintended leakage currents that do not contribute to the IC’s function, is a major problem that has been growing as process geometries shrink.

Drivers for Change

In addition to the mobile market, new markets such as datacenters, are increasingly concerned with power consumption numbers. According to Patrick Thibodeau of Computerworld, “U.S. data centers are using more electricity than they need. It takes 34 power plants, each capable of generating 500 megawatts of electricity, to power all the data centers in operation today”. The Internet of Things (IoT) and increased movement of all computer platforms to cloud computing has necessitated an increase in datacenter and server capacities. While ecological issues are always a concern, the cooling and power costs incurred for each additional MW of power consumed have become a real economic problem for business.

For these reasons, PCI Express designers are facing an ever-growing demand for lower consumption PCI Express devices. In order to optimize a PCIe design for low power, it is important to understand which power consumption figures are relevant for each type of application, and how they can be estimated.

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