Producing an Effective WLAN Prototyping Platform

The data routing between components is programmable on the central FPGA. The FPGA is the communication control center of the board. It contains a generic communication model that implements a programmable routing of payload data transfer and a control bridge between the application IP cores and the PC bus. This implies for the board routing that all I/O pins of all components are connected to the FPGA pins. Direct routing d oes not occur between two components.

Connecting all the pins to the central FPGA also eases the debugging process. For example a programmable logic analyzer unit on the FPGA can monitor the data on the I/O pins and store it in memory. This data can then be processed and analyzed off-line.

Integrating Application IP Cores
Once the generic platform is setup, it's now time to begin integrating application-specific IP cores, such as an 802.11 MAC, into the WLAN prototyping platform. Application IP cores are easily integrated by adding the footprints of the components related to the application IP cores in the basic board schematic and by connecting the I/O pins of the components to the central FPGA.

In the test and prototyping phase the application IP cores are evaluated separately and the system is built gradually. The communication model on the central FPGA is flexible to add new components in the system. The processor programs the communication links that are active.

The most co mmon interface used for the payload data is based on a synchronous first-in, first-out (FIFO) memory interface. Through this interface, common clocks are used for read and write together with empty and full flags.

The FIFO connected to the data output of a component is called an initiator while the FIFO connected to the data input of a component is dubbed a target. To transfer payload data between the initiator and target FIFOs, an arbiter is required to provide flow control in the WLAN prototyping platform. A shared payload bus is also needed

The flow control parameters of an initiator FIFO are the address of the target FIFO and the number of words that has to be transferred. The user can activate a communication link by programming these parameter. Once data enters in the initiator FIFO a request signal is sent to the arbiter to gain access to the shared payload bus. The arbiter sends a "grant" when the bus is free. If the target FIFO is not full, the data is transferred. If the FIFO is full, the data transfer is aborted without loss of data.

The arbiter is based on a round-robin system. It supports every clock cycle a data transfer requested by another initiator FIFO. This means that request signals of the components are handled sequentially.

Since components share the same bus, designers must turn to a high-speed bus when developing a WLAN prototyping system. For a Virtex-II FPGA with speed grade --4, designers can achieve a maximum bus bandwidth of 1.28 Gbps, which allows designers to connect up to 20 FIFOs on the same bus.

Interboard Payload Link
When developing a WLAN prototyping system, each board should have a standard PCI family connector so that it can be plugged into a slot on the backplane of the rack (Figure 2). The PCI bus transports data and control information between the boards in the rack.

A standard PCI bus is 32- or 64-bit wide and operates at 33 and/or 66 MHz. The access time to the shared PCI bus depends on the processing state of the PCI arbiter that grants the bus to a board in the rack. For WLAN systems, no latency is tolerated when transferring payload data between boards. This reduces the functionality of the PCI bus towards command and control instructions as well as to handling direct memory accesses (DMAs).

For payload data transfer between boards, designers should implement serial gigabit data links alongside the PCI bus. These data links can be achieved with off-the-shelf serial transmitters and receivers that currently support data rates up to 1.4 Gbps. The connections between the boards can be made at the front panel over twisted pair, coaxial cables, or fiber optic cables. Note: FPGA developers are also reacting to the need for gig abit links by integrating serial transceivers on upcoming FPGA designs.

Proving the platform for WLANs
Based on the platform concepts discussed above, designers can develop a library of boards for prototyping current and next-generation 802.11 WLAN systems. Let's see how.

In the physical layer of the WLAN standards three distinct parts can be recognized: the digital baseband modem, the radio front-end, and the medium access control (MAC). Typically, ASICs and FPGAs are used to implement the baseband functionality like the forward error correction (FEC) scheme and the modulator/demodulator. The analog radio front-end can be discrete or integrated as a system in a package. The MAC layer, which coordinates the access of multiple terminals to the common radio channel, runs in software on the DSP for the non-time critical functions and on a dedicated embedded MAC processor to handle the time critical functions. This results in a WLAN terminal platform set-up with a peripheral processor board a nd two boards that are built following the modular platform concepts. This platform will include a general-purpose digital board with programmable hardware for the baseband functionality and a general-purpose front-end board with a socket for analog front-end daughter boards. The terminal configuration is shown in Figure 3.

An implementation of the board library is done by IMEC for prototyping and demonstration of research results in the field of multimedia and WLAN applications. For the prototyping platform the CompactPCI interface was chosen because of its form factor 6U (width = 160 mm, height = 233 mm) and its robustness. The standard 19-in. rack with CD-ROM, power supply, and hard disk makes the platform transportable.

The IMEC boards are shown in Figure 4. In this figure, the modular board d esign with the common components like the central FPGA, the dedicated high-speed data links, the CompactPCI connector, and the power management unit are clearly visible on both boards. The layout and the critical routing between the central FPGA and the CompactPCI connector are reused for both boards.

The multi-million gate FPGA as application IP core makes the digital baseband board generic for use in different application domains like multimedia and WLAN. For WLAN, the baseband orthogonal frequency division multiplexing (OFDM) modem is mapped on the FPGA. An implementation of a 72-Mbps programmable WLAN OFDM baseband modem enhanced with adaptive loading functionality has been developed and mapped on a Xilinx XC2V6000 FPGA. The implementation consumes 48% of th e slice resources and 86% of the multiplier resources. The OFDM modem encompasses all functionality of the 802.11a physical layer except channel encoding/decoding. Adaptive loading is an enhancement on the standards to improve the performance without adding redundancy in the data stream. It exploits the frequency diversity of the channel by assigning an optimal bit loading to each subcarrier.

During prototyping, the RF front end is developed using a daughter card that plugs into the digital board. In this way, families of discrete and integrated front ends can be evaluated on the same digital motherboard. An extra benefit here is that noise coupling is avoided.

The digital board's central FPGA housed on the board with the RF front end can still implement system specific functionality to close the control loops over the analog and digital domains like automatic gain control (AGC) and I/Q imbalance compensation and to do up/downconversion to IF.

The 1.4-Gbps serial links are used to execute commu nication links across the boards. It's important to note that multiple antenna systems, such as SDMA and MIMO, can be prototyped by putting several front-ends and one WLAN baseband modem in the chassis.