How formal verification saves time in digital IP design

David Vincenzoni
EDN (November 10, 2015)

It is well known that the task of verification looms large in the design of digital IP, as well as the design of SoCs. The target is to reach 100% for both RTL code and functional coverage, minimizing the time spent obtaining it. The most widely used methodology is based on Universal Verification Methodology (UVM) random constrained tests (either System Verilog or e language) that permit the construction of complex tests in a relatively short time while stressing the RTL code and keeping track of functional coverage. Some verification engineers also use formal methodology for verifying a dedicated part of the block such as standard interfaces, which completes the verification of the IP.

This article will describe a different approach for digital IP verification based on formal methodology, exhaustively verifying the functionalities through the definition of properties. The formal approach has the advantage of avoiding development of test benches. This new flow has been used during the design of a digital IP and has proven to significantly shrink verification time.

Click here to read more ...