English
DFT strategy for IPs
Chintan Panchal, eInfochips
EDN (January 08, 2016)
Abstract
IPs (Building blocks of ASIC/SoC e.g. CPU, GPU) build and sign off in a wider sense. It doesn’t always mean Chip Timing, Design Rule Constraints & Power Closure of a block, but also refers to the creation of a layout/partition around the delivered build/sign off IPs/blocks. This would further refer to flows that are planned, library composition, various floorplan styles and shapes. The conflicts encountered in DFT and its equivalent solution, experienced during IP Block build (Hardening) are discussed in this paper. CPU - IP Block build (Hardening) accumulates many new DFT Flows & Methodologies for this purpose.
1- Introduction
1.1- SoC Methodology in Large Chip Design
Semiconductor companies typically face situations of unpredictable complexity during large chip design work which forces design engineers to switch to a fire-fighting mode rather than focusing on core design activities. While there are several methodologies used to tackle the challenges, System-on-chip (SoC) design, as a tried-and-tested methodololgy, has seen great success in large chip design. Simplicity is the key here: The SoC methodology involves the usage of predesigned and preverified blocks which are sourced from in-house teams or/and outside contractors which when combined together, becomes semiconductor intellectucal property (IP). This greatly reduces development test cycle time thus, ensuring faster time-to-market for the final product.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Complex SoC Testing with a Core-Based DFT Strategy
- Adding Cache to IPs and SoCs
- Optimize SoC Design with a Network-on-Chip Strategy
- Chiplet Strategy is Key to Addressing Compute Density Challenges
- Strategy To Fix Register-to-Register Timing For large Feedthrough Blocks Having Limited Internal Pipelines