From Here to 5G: A Roadmap of Challenges
Ron Wilson, Altera
Deploy 5G wireless networks by 2020! From research labs to service providers, these words have come to define a shared goal, almost a mantra. As a goal, the words justify all manner of R&D activities. But as a mantra, they betray a fundamental lack of definition. Just what is 5G? And what problems must we solve in order to deploy it?
On the surface, definition seems simple: 5G is the next generation of cellular technology after 4G. But peel back the surface, and you find something less appealing: a plethora of interests wrestling and squirming to promote their own product plans to ensure network support for their services, or merely to stave off obsolescence. Among their voices, you can hear demands for a diverse list of wishes.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Altera Hot IP
Related Articles
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- Key considerations and challenges when choosing LDOs
- Reliability challenges in 3D IC semiconductor design
- Handling the Challenges of Building HPC Systems We Need
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow