'Smart' verification moves beyond SystemVerilog 3.0

Raising testbench productivity with higher abstraction
Higher abstraction Hardware Verification Languages (HVLs) have already been proven to speed the development of the verification environment and go above and beyond HDLs or homegrown tools to improve verification productivity. HVLs help to create high quality tests faster.

Creating testbenches to verify designs require dynamic and high-level data structures, such as C/C++ classes and other inter-process communication constructs such as "events", "semaphores" and "mailboxes." The OpenVera HVL is an intuitive, easy-to-learn language that combines the familiarity and strengths of Verilog, C++ and Java, with add itional constructs targeted at functional verification, making it ideal for developing testbenches, assertions and properties. OpenVera accelerates the creation of verification environments and tests.

Figure 3 - VeraLite testbench constructs

Synopsys has donated VeraLite, a subset of OpenVera testbench constructs, to Accellera for standardization in SystemVerilog 3.1. These constructs enable engineers to write tests at a higher level of abstraction than offered by Verilog and make it easy for users to augment a Verilog-based testbench. Abstraction primitives of "semaphores", "lists", "mailboxes" and "classes" enable users to write high-level testbenches quickly instead of creating them from scratch. VeraLite also provides an easy interface to the device under test and can make use of SystemVerilog 3.0 interfaces. VeraLite extends SystemVerilog capabilities to allow the Verilog design community to easily take advantage of higher abstraction without the risk of moving to a new environment. It enables Smart Verification within the familiar and proven Verilog environment and significantly increases productivity.

Higher abstraction with assertions
Assertions are higher abstraction mechanisms that concisely capture design specification. They drive dynamic simulation and formal analysis to pinpoint bugs faster.

Assertions are a useful way to represent design specifications that are readable and reusable by multiple tools in the verification flow. HDL simulation tools use assertions to dynamically run "checkers" and "monitors" during simulation. Dynamic simulation of assertions allows for detecting bugs, whether simulating with random or directed tests. Functional coverage tools analyze simulation activity and provide information on coverage of functional test plans by reporting on coverage of assertions. Semi-formal tools use assertions to automatically generate tests to increase verification c overage. Assertions are also used as properties that formal analysis engines can use to exhaustively analyze and prove or disprove, greatly enhancing verification confidence.

In summary, assertions provide an evolutionary mechanism to greatly improve the productivity and confidence in the verification of complex SoCs.

The OpenVera Assertion (OVA) language was developed to accurately and concisely describe temporal behaviors that span multiple cycles and modules of the device under test. HDLs, such as Verilog and VHDL, were designed to model hardware behavior on single cycle transitions with procedural features. Such an execution model is not sufficient to efficiently specify multi-cycle temporal functions. With OVA, users can easily and intuitively express input/output behavior, bus protocols and other complex relationships of the design. Assertions captured with OVA are typically 3-5 times more concise than HDLs, enabling significant improvement in time spent writing and debugging assertions. OVA includes Intel's ForSpec formal temporal language.

Figure 4 - Assertions in OVA and Verilog

Synopsys has donated the full OVA language to Accellera for the unification of assertions into SystemVerilog. The OVA language is already compatible with Verilog expression syntax and semantics and can be easily used to enhance the procedural DAS assertion capabilities of SystemVerilog 3.0 to provide declarative assertion capabilities in SystemVerilog 3.1. "Templates" is an additional mechanism in OVA that allows users to create "assertion macros". Macros are a set of assertions that are independent of design signal names. Users can instantiate macros by connecting formal arguments of the macro with actual signals. Use of macros enables quick, easy and evolutionary application of assertions in a dynamic simulation environment.

Higher level C++ modeling
Many design teams today integrate the higher -level data structures provided by C/C++ in a Verilog verification environment using the Verilog Programming Language Interface (PLI), but are confronted with the complexity of writing and maintaining PLI routines. VCS DirectC provides the ability to easily mix Verilog and C/C++ constructs without the need of a PLI. Users can use C/C++ to define high-level algorithms and then call these C/C++ functions directly in Verilog code.

With concurrent modules of DirectC, existing C models can be brought and mixed with Verilog constructs of "timing," "concurrency," and "port interfaces." With direct data exchange between C/C++ and Verilog, DirectC provides the best possible performance. DirectC has been successfully used in a wide range of designs such as microprocessor, image compression and networking applications.

Synopsys has donated the DirectC/C-API to Accellera for standardization in SystemVerilog. A standard C-API provides ease-of-use, higher performance and tighter integration of C/C++ within the Verilog HDL. DirectC will extend SystemVerilog, and make it easy to use higher abstraction C/C++ models within Verilog. It allows much faster simulation of design models at a higher level of abstraction, while staying within the existing RTL verification and implementation methodology.

Coverage metrics drive verification closure
HDL code coverage and functional coverage are key elements of smart verification in measuring the quality of the verification environment and improving stimulus generation through pseudo-random test generation and directed test generation with semi-formal analysis.

Coverage provides insight into the effectiveness of test benches and allows designers to tune or redirect their tests to those areas of design that have not been adequately tested. Additionally, coverage ensures that simulation cycles are not wasted testing or exercising the same area or functionality over and over. Coverage metrics help to answer the question, "Are we done yet?"

Advanced simulators today natively generate comprehensive coverage data such as statements coverage, expression coverage, FSM coverage, observed coverage and assertion coverage. Various tools such as testbench automation, semi-formal analysis and graphical debug and analysis tools can use the coverage data generated by these engines to further enhance verification productivity and quality.

To facilitate consistent integration and tools interoperability, Synopsys has donated to Accellera a comprehensive API to access the coverage data that is generated by HDL simulation tools. Coverage API provides interfaces for third party tools to access simulator generated coverage data. Similar to the standardization of the Value Change Dump (VCD) file format created by third-party debug and analysis companiesa standard Coverage API will accelerate the development of third-party tools and applications that will use coverage information to enhance verification quality and productivity.

Jayant Nagda is group director of R&D at Syn opsys Inc where he leads Smart Verification R&D efforts. Mr. Nagda has more than 15 years of experience with EDA industry in software development, chip design, consulting services and management. Recently Mr. Nagda was Vice President at Zaiq Technologies Inc where he managed the Western region of that company's chip design and verification services business.