Tailoring is critical to successful RF analog CMOS chips

Innovative design often necessarily goes beyond prior art into uncharted places. The relatively recent adaptation of low-cost digital complementary metal-oxide semiconductor (CMOS) processes to high-frequency analog-radio devices (RF analog) is a significant example. Understanding the fundamental differences in signal type and circuit behavior is an important first step in reducing design risk.

Digital operation is conveniently bistatic, saturati on and cutoff. For the digital designer, the transition through the linear range between steady states is the undefined twilight zone to be gotten through as quickly and painlessly as possible. The time domain is analytically dominant. Signal amplitude is large, making low-level noise inconsequential. But signal power transfer is deliberately kept small. Ideally, no current at all would flow. Frequency response concerns are mostly limited to pulse edges and settling times.

In contrast, RF analog circuit elements live in the linear range, and in both the time and frequency domains. Saturation and cutoff are generally undesired; distortion is a forbidden zone. Device noise performance and linearity are at least as important as speed. Radio receivers, processing very small linear signals, and radio transmitters, generating quite large linear signal power, are sensitive to noise, thermal issues and complex impedance matching. The high signal power required for RF airwave transmission elevates power-adde d efficiency to a critical design concern.

Before trying to tailor a process design kit for RF analog devices, chip designers need to have the right EDA tool suite available. Simulation, optimization and parasitic extraction tools all need to be capable of frequency domain analysis. Parametric evaluation of noise performance, circuit stability and harmonic distortion must all be within the analytical capability of the EDA tools.

An assessment of available tool-set capability vs. immediate needs should be undertaken at the outset. Assessment should include training needs. The required investment in an EDA tool suite can be startling. EDA tool suppliers are always more than happy to advise on tool-set augmentation requirements and can offer valuable opinions and recommendations.

The procedure followed by foundry kit developers is logical and straightforward at first look. Fab the devices. Evaluate them by test under the expected range of operating conditions. Construct device models tha t reproduce the measured performance in simulations. And, voila, given due rigor, the kit is done. So why don't process design kits always work well right out of the box for RF analog circuits?

There are subtle sources of error that can be magnified in the sensitive world of RF analog circuits. At radio frequencies, test methodology and instrumentation can themselves influence, and potentially degrade, results and, importantly, repeatability of results. Without knowing the details of the foundry test plan, including the range of test conditions, statistical volume basis, equipment types and configuration, it simply isn't possible to know how closely the results will approximate those that could be expected in even a slightly different measurement environment. RF measurements are tricky.

Other factors including chip packaging or die probe effects, and their accompanying statistical variation, can accumulate with testing variables to occasionally produce sharply unexpected chip performance resu lts. The chip development's level of effort and cost make any uncertainty about a new process design kit unacceptable.

Calculating for uncertainty

Reducing uncertainty surrounding a new kit should come before developing any products using it. How is it done? The first step is kit and foundry device model soft validation. This involves running performance simulations on kit devices across the operating conditions and designated frequency range.

If the results fail to reproduce those claimed in the kit and foundry documentation, then the kit may produce circuits with unexpected performance attributes: a bad thing. This is a software exercise and, therefore, quick and inexpensive. No excuses. All critical parameters, including noise, should be evaluated. Noiseless element model performance would indicate a process-design-kit or foundry-device-model problem.

For parametric-value-dependent devices, including resistors, capacitors and inductors, create physical layouts to verify that the devices' geometries scale correctly from the schematic values. Also perform design rule checks to verify manufacturability of the devices defined from process-design-kit data. Running a statistically significant sample of values and configurations is a good idea.

What happens when kit soft validation fails? A process design kit is convoluted and based on a complex interdependence of data. Sometimes there are just bugs in it. The foundry kit's developers want to know about, and to correct, any bugs that appear. Treat them as teammates.

Of course, there are other potential sources of failure. EDA tool version compatibility should be checked. Kit revision status should be checked with the foundry. A three-way discussion between circuit designer, foundry process-design-kit developer and EDA tool developer is a healthy and productive thing, usually quickly resolving a kit's soft validation failure issues. It is in all parties' interest to improve the utility of kit and E DA tools.

A successful soft validation, when finally achieved, indicates that the device models, conceptual views, physical views and design tools are working together to produce an electronic construct that predicts successful results for circuit realization in silicon. But will it really be successful?

Hardware validation is the ultimate risk reduction. Build some test cells. And test them. Test cells for characterization can be as simple as a single circuit element, or as complex as you care to make them. For validating a kit, simple is better, with fewer potential variables to sort out. And the expense and investment of resources is smaller.

When characterization test results match those predicted by the foundry device models and process design kit, you are ready to make chips. If the characterization results do not match kit predictions, you have to roll up your sleeves. Why would they not match? Catastrophic failure usually submits to ordinary trouble-shooting. Bonding errors, p ackaging faults, test fixturing, test equipment failure or calibration and testing cockpit error are all customary causes.

When the device under test is functional, but slightly out of tolerance, real detective work is needed. There is just no substitute for a thorough grasp of RF test methods, and equipment behavior, when searching for sources of small error.