What's The Best Way to Verify Your SSD Controller?
Jean-Marie Brunet, Mentor, a Siemens Business
EETimes (9/26/2017 04:41 PM EDT)
To handle the complexity of hardware and software for advanced SoCs, design teams are employing hardware emulation for full chip functional verification of the controller SoC design as well as for the SoC's firmware.
To satisfy the world’s insatiable demand for data anytime and anywhere, storage devices are rapidly evolving and competition in the HDD and SSD storage arenas is getting fierce. At the heart of SSDs are complex controller SoCs that manage and monitor the integrity of incoming and outgoing data. These controllers also allocate data to a field/array of NAND devices, while monitoring the wear of the NAND to prolong the life of each storage unit. Each controller requires an algorithm and firmware to manage the complexities of writing and reading the various types of flash. That means controller designs not only have increasing hardware complexity, but software as well, and must communicate to a broad number of devices and protocols.
To handle the complexity of hardware and software for these SoCs, design teams are employing hardware emulation for full chip functional verification of the controller SoC design as well as for the SoC’s firmware. When choosing an emulator, teams invariably look at the available options of an in-circuit emulation (ICE) or virtual emulation methodology.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- PCIe error logging and handling on a typical SoC