Realizing 5G New Radio massive MIMO systems
Paul Newson, Hemang Parekh & Harpinder Matharu (Xilinx)
EDN (January 08, 2018)
16nm FinFET technology
The monolithic integration of high speed RF components benefits from the excellent analog transistor characteristics that can be wrung out of the 16nm FinFET process. The ON resistance of the transistor is extremely low, which allows implementation of wide bandwidth RF sampling signal switches with high precision. In turn this enables the integration of cost-efficient and power-efficient high speed comparators, amplifiers, clocking circuits, and digitally-assisted analog calibration logic, all with excellent characteristics.
The digital implementation in 16nm FinFET versus 65nm (typically used for analog RF components) results in more than 10× area reduction and 4× power reduction. Xilinx has innovated ideal design solutions to implement power integrity, digital calibration loops for high precision, and robust isolation strategies.
The digital-RF resources integrated in RFSoC are comprised of multiple channels of 6.4 GSPS DACs and 4 GSPS ADCs, integrated low phase noise PLLs and full complex mixers – 48-bit numerically controlled oscillators (NCO) for each DAC and ADC. The RF data converter arrays come with 1×, 2×, 4×, 8× interpolation and decimation filters and implement flexible FPGA fabric interface. In addition, the direct RF-DAC block implements quadrature modulation correction (QMC) and Sin x/x (Sinc) correction filters.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Xilinx, Inc. Hot IP
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow