COT: post design considerations

The cost benefits of COT will be maximized by taking advantage of the COT model's flexibility to optimize your technical solution and minimize the overhead required. But before a design group makes the move, it needs to take into account new manufacturing back-end issues and must evaluate cost models. Managing the post-tapeout technical, quality and logistical issues associated with manufacturing, packaging, assembly and test adds significant operational complexity for system-on-chip designs t ransitioning to COT.

The most significant difference between ASIC and COT is that ASIC vendors eliminate much of the flexibility that exists in packaging, manufacturing and test and subsume the details into one finished-product cost quote; COT requires the customer to manage the individual elements of the back end.

Historically, ASIC vendors have provided a catalog of packaging options from which customers could choose. Each package would typically have a minimum and maximum die size, and the customer would deliver a bonding diagram for approval before tapeout. Constraining the options to a few simplifies the ASIC vendor's package inventory, test and lead-time-related logistics.

The emergence of substrate-based packages such as ball grid arrays (BGAs) has provided a new level of flexibility in the packaging domain that COT users can leverage. There is really little cost difference between a 228-ball and a 231-ball package, for example, but the body size of the substrate and the thic kness (number of layers) can have a significant impact on the overall product cost. Consequently, COT design teams should work with their package/assembly house to design the best packaging solution to satisfy their technical and economic needs.

This effort is typically performed in parallel with the physical design of the chip. The flexibility in package design allows die optimization and reduced physical-design time, since the die does not have to fit into a pre-constrained existing package. Package and tooling costs typically are about $10,000 for plastic BGAs. Given the relatively low cost to customize a plastic BGA, opened-tooled BGAs are almost nonexistent.

ASIC vendors have strict test guidelines, which limit the quantity and construction of test vectors. Typically, they budget an allowable number of test patterns that a design team can provide, and they supply screening tools to force test generation into a lower-risk style. COT offers more flexibility, but it comes with more work. Whether you bring your engineering or production test in-house or simply outsource it, COT allows you to take full advantage of modern tester capabilities. If production test is being outsourced, the design house needs to select both a test house and a target tester platform at least three months before tapeout. If you are outsourcing test development, it is recommended that you work with a company that has nearby test development capabilities. Having a design team in the United States and a test development team in Korea, Singapore or Taiwan could be a very difficult thing to manage.

On the other hand, for production test, many companies want to have their assembly/test provider in the same country as their foundry to minimize the logistical delays of shipping material from one country to the next. First, identify the superset of testers that meets your technical needs. Different testers have varied test capabilities such as high-speed clocking and I/O, mixed-signal capabilities, memory capacity an d number of I/O channels. Next, rank these testers on two things — the per-hour cost of the tester and the total test capacity (number of testers) that your test contractor provides. You will need to select a test platform that can satisfy your technical, capacity and cost requirements. The ability to do multisite testing (for example, testing two or four devices in parallel) can change the economics in favor of a more expensive tester. Once the test platform is selected, the design team should determine the per-unit test cost of an integrated circuit for various test times (for example, 5 vs. 10 seconds) for both wafer sort and final test.

The IC cost model should budget appropriate costs for test. For instance, the cost model might allow 25 cents for wafer sort and 40 cents for final test. The test plan needs to be derived top-down with both economic constraints and quality goals in mind.

In the ASIC model, engineers typically only work from a total vector budget and some test guideli nes, which may not allow you to meet your quality goals. Test development begins with a good test plan and good design-for-test practices. The test plan should target a defects-per-million (DPM) quality level and define how that DPM level will be achieved given the cost-derived test times. For example, you can run patterns at high frequencies to minimize test times. In contrast, your ASIC vendor may have limited you to 10-MHz operation. Specific test time targets should be given for various test elements such as boundary scan, memory built-in self-test, scan, at-speed test and analog test.

Also, COT vectors do not necessarily need to follow "supersynchronous" guidelines, although reasonable limitations are necessary to ensure test robustness. Your test house will probably not specify these limitations, so you should derive your own — you do not want to encounter test issues that negatively affect yield or quality.

About one month before tapeout, you should begin working with your test h ouse on the load board and probe card design, a task that is usually invisible to most ASIC customers. You will want to pay careful attention to getting the load board design correct to minimize test debug issues once silicon is received. The load board and test socket should be ready about one week before the prototypes arrive, and open-socket test debug should be done in advance of real silicon testing. In the period between tapeout and arrival of prototype silicon, your design team should be getting all test patterns translated into the target tester format.

Tapeout issues

For design teams already experienced in doing turnkey ASIC designs with their own in-house physical designers, tapeout of a COT design won't be substantially different. For those without in-house physical design resources, a number of outsource companies offer physical design and tapeout services.

However, the COT tapeout process will be much different to those who are used to doing register tr ansfer-level (RTL) hand-off to an ASIC house and are new to in-house physical design. Many ASIC vendors provide netlist or RTL screening software for checking the general quality of the design, providing statistics on the design, and providing a general profile of the design's content. They may also provide vector screeners and other core tools to assist in the tapeout process. These tools are very useful, and may not be available from the COT foundries. Consequently, the COT design team will either need to purchase such tools or develop their own.

At tapeout, the design team will need to deliver physical design documents to the foundry of choice. These documents will typically require database details such as a list of layer assignments (e.g. Layer 50 is contact), the design coordinates, the libraries used, any special cells, any physical design rules to be waived, process control monitor (PCM) requirements, wafer-handling instructions, and any special processing or manufacturing instructions.

Typically, the foundry is asked to stage half of the prototype wafers at Metal1, just in case a bug fix or ROM spin is required. Many foundries give COT teams the option of delivering GDSII databases or masks. If GDSII is delivered, the customer will need to select a vendor for fabrication of the masks, or else the foundry will choose one. For a given foundry technology, there may be one to three qualified mask vendors. Keep in mind engineering lead times for COT foundries are typically longer than for ASIC houses. As such, you will need to manage all post-tapeout schedule issues carefully. Some foundries will offer "hot lot" or "super hot lot" services, on an as-available basis whereas ASIC vendors typically run all prototype lots at "hot" status. You may also be able to expedite mask development.

To further expedite the COT tapeout process, you should work with the foundry's mask tooling department to preapprove any custom cells, especially if they are using different design-rule checking (DR C) software than you. In the ASIC environment, the responsibility for product engineering functions such as yield optimization and quality-level improvement are performed and managed by the vendor. The profitability of the ASIC vendor will be greatly affected by the yield, while the ASIC customer will only see indirect effects such as slippage in shipment dates or DPM.

Foundries typically use one of two cost models, either the Murphy Model or the Bose-Einstein model. COT users must get their process-specific defect density and complexity factors from their foundry. In COT, whichever model is used to predict die cost, you will need to do some work to reach acceptable yield. Product engineering is a key contributor to device profitability. Once the final production test is debugged (on packaged parts), a subset of that test is used for wafer sort. The test debug process is not substantially different for COT versus ASIC, except that for COT, you will need to pay more attention to the yield metrics, inc luding PCM data. You should screen the PCM data and chart key parameter trends to understand the quality of each lot. Commercial tools exist for this purpose. The sort yield from your first wafer lot may start 10 percent or more below the yield predicted by the model.

You will need to verify the robustness of the test program. This is where the test rules you enforced on your designers will help. Once the wafer-sort program is stable, you should routinely send the wafer map data for each production lot to the foundry to allow it to improve the manufacturability of your design. Some test houses and foundries have direct Internet or FTP connections and can automate the routine transfer of this information. Once the final production test program is in place, device characterization should be run. ASIC vendors historically provided a lot of timing guard band to their libraries and processes, so most vendors have not routinely performed device characterization.

However, in COT it is useful to pr oduce a corner lot, which varies three or four process parameters in various combinations (such as every wafer in a 25-wafer lot will have a different characteristic). A few parts from each of these wafers will be tested across minimum and maximum voltage and temperature. Shmoo plots will be generated for several digital parameters to verify the robustness of the device and test program. Similarly, histograms will be generated for analog parameters.

Running AQL (acceptable quality level) sample lots through additional bench or product testing can be used to verify target DPM levels. Wafer sort and final test yield are a direct reflection of process quality and assembly quality, respectively. Managing these yields with the foundry and assembly house is a constant chore for the COT consumer, and companies do exist which offer to help manage this task.

Once a part is in production, quality works backwards through the flow. A DPM problem in the factory line will need to be diagnosed. The product or design engineering team will need to determine if the problem was due to a test escape during the IC test, to handling, to a process reliability issue, or some other situation. Resolution of the problem may require interaction with all of your suppliers, so it is very important to select suppliers that will cooperate on yield improvement and defect resolution.

Wafer requirements

In any case the first level of failure analysis (FA) is the COT customer's responsibility, and extensive FA will need to be outsourced. Many ASIC companies offer FA services as part of their operation. With ASIC, when you need 50,000 parts, you give a purchase order for 50,000 parts to your ASIC vendor. With COT, it's not that straightforward. Assuming a make-to-order model (no inventory), you will first need to translate your order requirements to wafer requirements based on the expected total yield (wafer sort and final test yield). Since the yield will change slightly over time, this will need t o be taken into account.

For example, suppose you need 50,000 parts, you have 1,000 gross die per wafer, a wafer sort yield of 75.7 percent and a final test yield of 99.5 percent. You will need 50,000/(1,000 x 0.757 x 0.995)=66.4 wafers. Since wafer lots are usually multiples of 25 wafers, you will have to start 75 wafers, and the excess material may need to be inventoried either as wafers or finished goods.

You will almost never get exactly the number of parts you require. For example, if you plan for 50,000 parts, you may get 51,327 or 49,368. To this end, you should expect to have some interesting conversations with your product sales department as well as your finance department regarding the fulfillment of both customer and supplier purchase orders. When too much material is produced, you have inventory, and this will need to be managed as part of the overall work in progress (WIP).

Proper forecasting and scheduling of material in the COT model can be a significant challenge. Y ou need to provide forecasts for foundry, assembly and test. Each supplier may have their own forecast requirements, and the commitment implications of a forecast may vary between suppliers. For example, some suppliers may start material only when a purchase order is received while others may start based on a forecast. A complete product requires the COT customer to be responsible for securing ample capacity for foundry, assembly and test, and lead times will blow up if any one of these items is in short supply. For example, if your assembly house doesn't have enough mold-compound for your plastic BGAs, you will be waiting for your ICs.

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