Better Benchmarks through Compiler Optimizations: Codasip Jump Threading
By Codasip
September 9, 2019
The architectural efficiency of embedded processor IP is measured by a small set of industry standard benchmarks, that even though often bear little correlation to real workloads, continue to persist. The most popular benchmarks are Dhrystone and CoreMark.
An interesting observation regarding these test suites is that the performance numbers continue to improve for a given architecture, even when the architecture itself remains unchanged. The reason for this improvement is the focus on continuous compiler optimizations intended to improve the performance of a given benchmark.
The RISC-V community makes extensive use of open source compiler technologies. The most widely used C/C++ compilers today are GCC by the GNU Project and Clang by the LLVM project.
Each compiler comes with a set of advantages and disadvantages, and most users of RISC-V today employ the GNU toolchain. However, the Codasip C/C++ compiler is based on LLVM. LLVM is an umbrella project that hosts a set of related low-level toolchain components (assemblers, compilers, debuggers, etc.). LLVM and its C/C++ frontend, Clang, provide a number of benefits over GCC, specifically faster compilation and lower memory usage, expressive diagnostics, and modular library-based architecture that allows easy customization and addition of custom extensions in the form of new architectures, instructions, and optimizations.
However, one of the stronger points of GCC is that its jump threading pass is more powerful than the same pass in LLVM, which also has difficulties in threading jumps used in CoreMark benchmarking. To mitigate it and improve our own LLVM solution, Codasip developed an innovative implementation of jump threading that helped us achieve significantly faster code and better CoreMark results.
These techniques are described in detail in our latest whitepaper.
If you wish to download a copy of this white paper, click here
|
Codasip Hot IP
Related Articles
- Casting a wide safety net through post processing Checking
- Creating SoC Designs Better and Faster With Integration Automation
- Reducing Power Hot Spots through RTL optimization techniques
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- A formal-based approach for efficient RISC-V processor verification
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
E-mail This Article | Printer-Friendly Page |