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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
RISC-V's CPU Verification Challenge
By Bipul Talukdar, SmartDV
RISC-V is gaining attention throughout the semiconductor industry. It offers the lure of an open-source solution that anyone can leverage to create their own CPU or custom accelerator.
Of course, dig deeper and challenges emerge. RISC-V is new and does not have the benefit yet of years of field-proven experience. This means that a carefully chosen and executed CPU verification strategy is essential. It also means that the availability of a “golden reference model” is a critical component that must be secured. Without a known good reference, it is impossible to have confidence in verification results. Having a custom instruction set simulator (ISS) is vital to success.
Proper verification of a CPU design and associated instruction set architecture (ISA) is one of the most challenging activities that a CPU core engineering group must tackle. Unlike fixed-function designs or blocks, a CPU is programmable and meant to perform many different tasks. Ultimately, it is defined by the breadth and depth of its ISA and the different ways in which programmers leverage the ISA. Even using supercomputers, achieving 100% verification of the CPU considering all combinations of instructions, memory utilization, data patterns, and the like would take many thousands of years.
Instead, CPU verification groups must work smarter and focus on doing “enough” verification to catch the most likely problems. The definition of “enough” changes based on the specific CPU and ISA –– such as a broad set of capabilities versus a narrow-focused set –– and the end-application market that could be safety-critical or general-use, for example.
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