Are you optimizing the benefits of cloud computing for faster reliability verification?
By Matthew Hogan and Derong Yan (Calibre Design Solutions division of Siemens EDA, a part of Siemens Digital Industries Solutions)
EETimes (September 28, 2021)
Design complexities and time-to-market pressures compel companies to find innovative ways to leverage available resources. Cloud computing provides a scalable and sustainable platform that can significantly improve runtimes in demanding EDA compute tasks like Calibre PERC reliability verification flows. We demonstrate how companies can use cloud resources to increase productivity and expedite turnaround-times, then use that data to understand the cost/benefit relationship of cloud computing and determine the optimal configuration that provides the greatest returns.
In today’s fast-moving industrial and consumer products, integrated circuit (IC) design companies know that getting their designs to market on or ahead of schedule is crucial to maintaining or gaining competitive success. However, they also know that the performance of their products after they hit the market is equally critical. Getting a product to market, only to have it fail to deliver the performance or product life the advertising promised, is the nightmare companies never want to have.
For that reason, reliability verification is now an essential part of the IC design and verification flow. The scope and complexity of reliability issues, such as electrostatic discharge (ESD) and latch-up protection, has grown substantially as designs moved to the most advanced process nodes (figure 1). In response, most foundries now provide some form of reliability design rules, which are enabled by electronic design automation (EDA) companies in the form of automated reliability verification tools and checks [1-3].
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Early Interactive Short Isolation for Faster SoC Verification
- Design-Stage Analysis, Verification, and Optimization for Every Designer
- Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- Out of the Verification Crisis: Improving RTL Quality
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)