Chiplet Strategy is Key to Addressing Compute Density Challenges
By Balaji Baktha, Ventana Micro Systems
EETimes (September 28, 2021)
Data center workloads are quickly evolving, demanding high compute density with varying mixes of compute, memory and IO capability. This is driving architectures that are moving away from a one-size-fits-all monolithic solution to disaggregated functions that can be independently scaled for specific applications.
It is imperative to adopt the latest process nodes to deliver the needed compute density. However, doing so with traditional monolithic SoCs presents an inherent disadvantage due to escalating costs and time to market challenges resulting in unfavorable economics. To address this dilemma, chiplet-based integration strategies are emerging where compute can benefit from the most advanced process nodes, while application-specific memory and IO integrations can reside on mature trailing process nodes.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Key considerations and challenges when choosing LDOs
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- The evolution of embedded devices: Addressing complex design challenges
- Programmable Logic Holds the Key to Addressing Device Obsolescence
- Addressing Clock Tree Synthesis Challenges
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)