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The case for SystemC
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The case for SystemC
By Joan Bartlett, EEdesign
March 7, 2003 (1:08 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030307S0020
The challenge to produce higher density chips requires a change in the decade-old system design flow. We are at an inflection point similar to the move from schematic-based to hardware description language (HDL)-based design. Three major problems need to be addressed to enable engineers to design and implement the multi-million gate chips forecast by Moore's Law: But, incremental changes to these languages and tools do not offer an encompassing solution to the problem at hand. Plus, changes in som e cases can obscure the power of the existing products to meet the needs they address. Verilog is a well-established register transfer level (RTL) language for simulation and synthesis. Does a Verilog that includes mailboxes and semaphores really add value to RTL synthesis? What is needed is a language that is based on an object-oriented foundation, provides fast simulation performance and can easily be used for hardware/software integration. SystemC, the library extension to C++, provides all three answers. SystemC is a naturally object-oriented language that allows designers to use familiar hardware concepts such as modules and interfaces to model their design at high and intermediate levels of abstraction. Since SystemC is C++, simulation performance is fast. The high abstraction modeling and increased performance enables the creation of software development platforms much sooner in the design process, allowing software integration and testing at the earliest possible point. This all adds u p to greater parallel development efforts resulting in earlier time-to-market and increased quality of the final product. The issue with SystemC is not whether it is technically able to meet the needs of next-generation designs, but how to harness its power and produce a methodology with the right tools to enable a SystemC design flow. The SystemC language is free and can be downloaded from the Actis Design.
The EDA industry has tried to address these issues with extensions to existing languages (Verilog 2001, SystemVerilog) and introducing verification specific languages (Vera, e) with some incremental success or at least hope of success.
