Why Low Complexity Video Coding is Answer to UHD TV Success
By Rick Clucas, V-Nova
EETimes (October 28, 2021)
Ever since regular TV broadcasting began by the BBC from my home town London on 26th August 1936, the broadcast industry and the technology ecosystem around it has been continually striving to improve it and make it look better. However, in recent years we have failed to upgrade traditional terrestrial broadcasting to ultra-high definition (UHD), with the consequence that most people who have been buying UHD TVs have never watched any actual UHD TV content on them!
The main reason UHD TVs have been a great success for TV manufacturers is because they have the opportunity to sell premium products that for the same screen size actually cost them less to manufacture than a full HD panel. This is because the display production yield for UHD is greater than full HD due to there being four times as many pixels for the same screen size, meaning the allowed percentage of non-defective pixels is much easier to meet.
Sadly, as of 2021 UHD has remained impractical for broadcasters, since current video codecs just consume too much precious spectrum. In particular, it doesn’t make economic sense to broadcast UHD, since
- the bandwidth requirements of UHD channels are too high, and
- in addition, they would still have to separately broadcast a full HD version for the large number of viewers who don’t have a UHD TV.
Another dimension is that the lack of UHD content has made it easier for new OTT services to enter the market with higher-quality content, putting further pressure on traditional broadcasters’ revenue streams.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Convey UHD 4K Video over 1Gbit Ethernet with the intoPIX JPEG 2000 "Ultra Low Latency" compression profile
- The VP8 video codec: High compression + low complexity
- Hybrid Hardware Architecture for Low Complexity Motion Estimation Algorithm
- The need for speed in low latency video system designs
- A Low Complexity Parallel Architecture of Turbo Decoder Based on QPP Interleaver for 3GPP-LTE/LTE-A
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)