NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
The case for de-integrating embedded Flash
By Sandeep Krishnegowda, Infineon Technologies
embedded.com (August 19, 2022)
When Flash is external to the SoC, memory is no longer a limiting factor. Developers can select a best-in-class SoC based on its performance and scale Flash density independently. Being able to right-size Flash memory also reduces system cost and footprint.
For decades, the prevailing strategy for innovating electronic system design, regardless of industry, has been to integrate more capabilities and greater memory capacity into fewer chips. This has led to the rise of complete system-on-chip (SoC) architectures, enabling complex embedded systems to be designed around a single chip. Complementing integration has been increasingly tighter manufacturing process nodes and shrinking die size. The result is smaller SoCs capable of higher performance at a lower cost.
The increased capabilities enabled by integration at the chip level has led to the consolidation of features and capabilities at system level. For example, in today’s evolving autonomous vehicle architectures, instead of comprising several distinct subsystems in a distributed architecture, functionality is now being consolidated into a single vehicle control platform (VCP). These platforms offer greater efficiency, control, and reliability, as well as optimized power management and overall reduced system footprint and weight.
Centralized computing is possible through the increased compute power of integrated SoC architectures. And, as vehicles become more intelligent, they require greater processing resources within the vehicle. In fact, cars are going to need significantly more intelligence – and data storage – to move to the next level of autonomy.
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