ggNMOS (grounded-gated NMOS)

By Sofics

ggNMOS intro:

For decades, a traditional workhorse device for ESD protection for standard applications in CMOS technology has been the grounded-gate NMOS device (ggNMOS).

Nevertheless, we have been explaining the operation of this device countless times, including as recently as 3 weeks ago. So, it is time for a short blog article. The schematic of a ggNMOS and its typical ESD I-V characteristic are sketched in Figure 1.a and b.

Figure 1: Figure 1: ggNMOS schematic (a), and the ggNMOS IV characteristic (b).

How does NMOS snapback work?

To understand the physical operation, one should study the silicon cross-section of the NMOS (simplified in Figure 2.a), and consider the equivalent bipolar schematic that one can uncover (Figure 2.b).

Figure 2: NMOS cross-section (a) and the equivalent bipolar schematic (b).

When increasing the drain/collector voltage versus the grounded source/emitter/bulk a reverse voltage will build up across the drain to the substrate junction in Figure 2.a, which is also the collector/base diode in Figure 2.b. Until that diode breaks down (assuming no punch-through occurs) there will be no current flowing through the reverse diode or junction. At some point, the reverse diode will breakdown and current will flow in the depletion region of the diode. Carriers will be accelerated in the electric field and create an avalanche effect when knocking into other fixed carriers. This is illustrated in Figures 3 a and b. As the reverse voltage is increasing, the current will increase rapidly.

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