Soft errors affect SRAM's future

Soft errors affect SRAM's future
By David Lammers, EE Times
May 13, 2003 (5:11 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030513S0045

AUSTIN, Texas — The impact of soft error rates (SER) on SRAM memories will increase as scaling continues, contributing to a shift away from stand-alone SRAMs to DRAMs, a panel of memory experts argued.

Speaking today (May 13th) at the MemCon Boston conference, organized by Denali Software, Inc. (San Jose, Calif.), the panelists reached general agreement that as scaling proceeds past the 90-nm node, the smaller amount of charge on SRAM cells will make them more vulnerable to soft errors caused by cosmic alpha rays as well as neutrons emitting from the packaging.

Mike Pearson, director of networking business development at Samsung Semiconductor, Inc., said Samsung controls about one-fourth of the total SRAM market now, and will continue to be aggressive in the SRAM business. However, SRAMs gradually will be sold into the "very low-power and very, very fast" corners of the total memory market.

In cell phones, for example, SRAMs are giving way to pseudo SRAMs, essentially a DRAM with SRAM-like peripheral logic. And in networking, low-latency DRAMs are encroaching on the SRAM market as well, he said. Embedded DRAM, which continues to be relatively expensive, is another contender taking share away from discrete SRAMs.

Pearson said that due to alpha particle-induced SER issues, Samsung recommends to its customers that if they choose to implement a memory bus that is less than 72 bits wide "that they keep an eye on soft error rates. If they are using 18 to 36-bit-wide buses, there are steps they need to take, because the reality is that the SRAM cell is susceptible to SER."

Thomas Pawlowski, senior director of architecture development at Micron Technology, Inc. (Boise, Idaho), said that SRAMs are as much as 1,000 times more susceptible to SER than are DRAMs. Micron tests various company's DRAMs and SRAMs, using stress testing equivalent to 1,000,000,000 hours of operation.

Shigeo Ohshima, a DRAM technical marketing manager at Toshiba C orp., said Toshiba's roadmap for SRAMs is clear through the 90-nm technology node, which lasts through 2006. However, after that, he said soft error rate and other issues will put "severe" pressure on SRAMs throughout the 65-nm node.

Pawlowski said the SRAM market also is coming under pressure because of the ability to extend DRAM technology. He said Micron has research underway that may allow DRAM refresh rates to be as long as two to four weeks, which compares with about 60 milliseconds now.

The Micron senior fellow also said the Micron is working on ways to keep logic and memory on separate die, allowing each to be made with the optimum process technology. Though Pawlowski did not elaborate, he appeared to be referring to 3D interconnect technology, in which logic and memory die can be connected with thousands of very short interconnects linking two or more dice. He said the technology will impact the market in two to three years.

The remarks of several of the panelists were skewed toward thei r flavor of the low-latency DRAM. Micron and Infineon Technologies are pushing their RL (reduced latency) DRAM for networking applications, and Toshiba is selling the Fast Cycle (FC-DRAM) memory into that market as well. Micron recently decided to withdraw from both the SRAM and CAM (content addressable memory) markets.