Adding Cache to IPs and SoCs

By Andy Nightingale, Arteris
Electronic Design, June 27, 2024

Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache coherency and power consumption.

What you’ll learn:

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip.
Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU clusters and IP blocks.
Implementing cache memory, including L1, L2, and L3 caches, addresses the need for fast, local data storage to accelerate program execution and reduce idle processor time.
CodaCache enhances data throughput, reduces latency, and improves energy efficiency in SoC designs.

Designers of today’s systems-on-chips (SoCs) are well acquainted with cache in the context of processor cores in central processing units (CPUs). Read or write access to the main external memory can be time-consuming, potentially requiring hundreds of CPU clock cycles while leaving the processor idle. Although the power consumed for an individual memory access is minimal, it quickly builds up when billions of transactions are performed every second.

For context, a single 256-bit-wide data channel running at 1.5 GHz will result in approximately 750 million transactions per second, assuming each transaction is 64 bytes. Multiple data channels will typically be active in parallel, performing off-chip DRAM access.

When a program accesses data from one memory location, it typically requires access to other locations in close proximity. Furthermore, programs usually feature loops and nested loops in which multiple operations are performed on the same pieces of data before the program progresses to its next task.

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