AI-driven SRAM demand needs integrated repair and security

By Meng-Yi Wu, eMemory
embedded.com (July 15, 2024)

Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.

Along with the rise of the internet of things (IoT), mobile devices, and edge computing, the boom in AI-enhanced features has enabled the addition of even greater functionality in applications such as intelligent sensing, in-vehicle driver assistance (ADAS), and voice recognition, all of which require the use of increasingly larger training models.

However, as the progress of CPU performance slows, new ideas to reduce the I/O and data loading on CPUs are becoming more popular. These include such solutions as DPU or PIM (process in memory) architectures, as well as the introduction of hierarchical data processing. However, as more CPUs are required for hierarchical processing, there is a corresponding need for more SRAM caches to serve these high-speed CPUs. Thus, the increasing popularity of AI applications and DPU architecture implementations has led to growing demand for higher SRAM densities

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