Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
By Enrique Martinez, EnSilica
All About Circuits (November 12, 2024)
This article explores the history of the 600 nm process, the reasons behind its phase-out, and what the industry has to look forward to as smaller, more efficient chips become the new standard.
The semiconductor industry is continuously evolving, and while evolution is a good thing, it also means that some well-established technologies are inevitably approaching the end of their end of life. As those in the industry will know, many foundries have issued last-time buy notifications for their 600 nm ASICs as they pivot toward more efficient, smaller geometry nodes.
This will force companies in the automotive, aerospace, defense, telecommunications, and consumer electronics sectors to rethink their semiconductor designs. However, as we’ll discuss, that isn’t necessarily bad news.
E-mail This Article | Printer-Friendly Page |
|
EnSilica Ltd. Hot IP
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)