What is JESD204C? A quick glance at the standard

By Chip Interfaces

JESD204C standard at a glance

The JESD204C standard enables establishing high-speed serial links between a Controller and ADC and DAC converters. JESD204C was first published in December of 2017 as an iteration of the JESD204B Standard published six years prior in July 2011. It retains backwards compatibility with its predecessor while introducing multiple new neat features and faster line rates. An incremental update JESD204C.1 was published in December of 2021 slightly increasing the maximum line rate. In this article, we will introduce the JESD204C.1 standard and the new capabilities.

Deterministic Latency

Deterministic Latency, a key feature first introduced in JESD204B, is a capability continued in the JESD204C iteration. Deterministic Latency allows for the Link Latency to be constant despite latency variations on the serial link, along with the ability to finely adjust it to meet broad system synchronization requirements. Deterministic latency is achieved by the use of a buffer in the receiver which compensates for latency variations on the serial link and often serves the dual purpose of de-skewing lanes. The new 64b66b link layer supports deterministic latency with the use of the SYSREF signal which is distributed to all elements of the system and used as a common timing reference.

Key features of JESD204C

A new line rate of 32.5 Gbps is available in JESD204C thanks to the use of the new 64b66b encoding in the Link Layer (PCS). Scrambling is made mandatory with the 64b66b encoded since it appends 2 extra bits and leaves the data unaltered in contrast to the use of special codes in the 8b10b encoding, it allows for reducing baseline wander and ensuring DC balance, as well as helps with the receiver synchronization and block alignment. When using the 64b66b Link Layer the receiver is self-synchronizing to the transmitter stream and no additional handshaking or sync signaling is required.

The 2 added bits in 64b66b encoding are firstly used for finding block boundaries, as these will always be encoded as 10 or 01 they are made easy to identify in the scrambled data stream by the process of position elimination. On top of this, the 10 or 01 values encode a 1 or a 0 and are grouped into sets of 32 to create an additional data channel for Cyclic Redundancy Check (CRC3, CRC12), Fire Code Forward Error Correction (FC-FEC), or a Command channel (CMDC). Within the 32-bit word, there are also bits reserved for Extended Multiblock Framing, which is the major framing structure replacing Multiframes from JESD204B.

Chip Interfaces’ JESD204C IP Core is an established, highly optimized, fully featured, silicon agnostic for ASIC and FPGA, interoperability tested and silicon-proven implementation of the JEDEC JESD204C.1 standard. To learn more about our JESD204 C IP and how we can enable your project, please contact sales@chipinterfaces.com.