English
Why RISC-V is a viable option for safety-critical applications
By Jay Thomas, technical development manager, LDRA
EDN (February 14, 2025)
An intro to RISC-V
As safety-critical systems become increasingly complex, the choice of processor architecture plays an important role in ensuring functional safety and system reliability. Consider an automotive brake-by-wire system, where sensors detect the pedal position, software interprets the driver’s intent, and electronic controls activate the braking system. Or commercial aircraft relying on flight control computers to interpret pilot inputs and maintain stable flight. Processing latencies or failures in these systems could result in unintended behaviors and degraded modes, potentially leading to fatal accidents.
The RISC-V architecture’s inherent characteristics—modularity, simplicity, and extensibility—align with the demands of functional safety standards like ISO 26262 for automotive applications and DO-178C for aviation software. Unlike proprietary processor architectures, RISC-V is an open standard instruction set architecture (ISA) developed by the University of California, Berkeley, in 2011. The architecture follows reduced instruction set computing (RISC) principles, emphasizing performance and modularity in processor design.
RISC-V is set apart by its open, royalty-free nature combined with a clean-slate design that eliminates the legacy compatibility constraints of traditional architectures. The ISA is structured as a small base integer set with optional extensions, allowing processor designers to implement only the features needed for their specific applications.
This article examines the technical advantages and considerations of implementing RISC-V in safety-critical environments.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- Demystifying MIPI C-PHY / DPHY Subsystem
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution