EAVS - Electra IC Advanced Verification Suite for RISC-V Cores

A white paper written by Electra IC Team; Merve Eyüboğlu, Murat Tökez, Ibrahim Mouamar Ali Ahmed, Melike Atay Karabalkan, and Berna Ors.

Electra IC Advanced Verification Suite (EAVS) for RISC-V Cores is a powerful and flexible RISC-V core verification environment. It integrates a UVM testbench, Instruction Set Simulator (ISS), and automated validation tools to ensure compliance with RISC-V standards.

With randomized test generation, parametric flexibility, and seamless core integration, EAVS-DV enhances verification efficiency and accelerates development. Designed for adaptability, it supports various RISC-V implementations, providing a scalable and reusable solution for next-generation processor validation.

To read the paper, click here.