Custom SoC designers must consider interconnect effects

Prior to 0.25-micron technology, on-chip metal interconnect did not have a significant effect on chip performance. Design performance was fairly easy to predict from interconnect look-up tables. With input/outputs (I/Os) running in the 100 MHz range, system simulation requirements were low at the chip-to-pc board level.

It was expected that the delay effect of metal interconnect would increase as technology scaled but few designers fully anticipated the degree of complication it would add to the design process and the extent to w hich tool flows had to be augmented to check for these potential killer effects.

Gradually, the signal integrity and performance of interconnect on die and in the package have become more significant. Today, at 0.13-micron and lower, it manifests itself in several ways:

• The interconnect in high-performance package substrates is complex and has to be modeled and simulated just like any other component in the SoC.

• High-speed serializer/deserializer I/O cells are sensitive to configuration. Models for 4-channel, 16-channel and different Rx/Tx physical relationships differ. The I/O path from die through the package substrate to the pc board has to be re-modeled for every different design implementation

• Metal interconnect has become narrower but its thickness has not scaled at the same rate. This results in less capacitance to ground and more coupling capacitance.

• The result of the small metal cross-sections and thin low-dielectric insulators is that any pro cess variations in the interconnect can have a large impact on system performance.

• Higher-frequency operation and relatively thicker metal make the inductance effect more significant.

The effect of interconnect delay due to resistance/capacitance was expected and is easily modeled. Other effects can degrade signal integrity and have to be taken into account during the development process. If not, the design could have crosstalk and noise problems.

Prevention early in the design process is much cheaper than trying to detect and fix the problem at the end of the design process. To handle the potential interconnect problems successfully, deep-sub-micron custom SoC design flows need to incorporate both prevention and post-layout correction design methodologies.

Virtually all SoC designs use custom-designed multi-layer substrate ball grid array (BGA) or flip-chip BGA packages. The substrate needs to be designed with a high degree of trace matching and screening to preven t noise, cross-talk and IR-drop effects.

For prevention purposes, the signal integrity designer needs an accurate package model, usually HSPICE or IBIS, to simulate the cell from the chip, through the package to the pc board and back to ensure that the design will meet the specification. For multi-layer packages, 2D- and 3D-field solving tools may be needed.

IR-drop analysis has to start at the block floor planning stage and continue though the hierarchical planning. For example, Toshiba's team uses an internal tool called IREST at this stage. It allows fast estimation of IR-drop and highlights potential problems in the power grid and package resistance. The tool takes into account the metal plan, including number of layers and track-width/thickness, etc. During the early design planning stage, prevention options include the ability to change the number of interconnect layers, change the power and ground scheme and related number of I/O cells, choose the optimal metal thicknesses and add mor e power planes to the package substrate design.

Also, as part of the simultaneous-switching outputs (SSO) prevention methodology, high-speed I/O designers need to add decoupling capacitors to the on-chip I/O supply lines to minimize the effect of dynamic IR-drop. Later during the physical design cycle and for the post-layout correction stage, more accurate analysis can be made using tools such as the Cadence VoltageStorm power grid verification solution.

In addition to using IREST and VoltageStorm, normal SSO analysis tools are used to check for ground bounce and I/O switching noise problems that will cause performance loss. Prevention also includes checks for any potential electromigration problems that could affect reliability.

Cross-talk issues

An increased number of interconnect layers with relatively thicker, narrower tracks on the die and the package coupled with higher clock speeds and faster signal edges have resulted in greater potential for a design to have cross-talk and signal integrity issues. The inductance of the interconnect is becoming more significant. For frequencies of less than 500 MHz, resistance in normal metal interconnect layers is high enough to mask the inductance factor. For higher frequencies, tools need to include inductance in their extractions and calculations. This is most significant on the low resistance I/O redistribution layers where high speed I/Os are also present.

Cross-talk can kill a design due to noise/glitch spikes, cross-talk delay and double clocking. For the prevention stage, one option is to use signal integrity aware routers such as Magma's BlastFusion with BlastNoise. This class of tool applies special rules to clock signals and inserts clock buffers as required to minimize cross-coupling and noise.

At the end of the physical design process in the correction phase, verification tools like the Cadence CeltIC signal integrity solution should be used in the design flow.

As wires becom e narrower and dielectrics become thinner any process variations start to have a higher impact. The interconnect on one side of the chip can be slower than wires on the other side of chip.

The prevention methodology employs adequate manufacturing margins. Extensive characterization of the process corners is required to create these margins for manufacturability and at the same time minimize the effect on design performance. The resulting derating factors then have to be accurately reflected in the timing equations used in the design.

One manufacturing technique that minimizes metal interconnect delay uses several different interconnect thicknesses on a given die. With an advanced process, it is normal to use three or four different width/thickness metallization options during the build up of interconnect on the chip. On top of the first local routing layer will be a varying mixture of intermediate routing layers followed by the semi-global and global routing layers. The number of layers used will vary and is dependent on the design's power and performance needs.

If the prevention methodology is inadequate, interconnect modeling problems must be fixed post-layout in the correction phase. This is very expensive and will lengthen the design cycle significantly. It could require making custom characterization wafers and process tuning — a deadly solution for today's high-end manufacturing lines. A prevention methodology has to be the main solution and this implies a great deal of up-front process characterization work before the models are used in design.