Signal integrity a challenge in IC design

Timing is dominated by interconnect-dependent RC delay in deep-submicron designs. Previously dismissed as secondary effects, cross coupling, via resistance, inductance, power integrity and wire self-heating become first-order design parameters. Design flows using various point tools fail to predict final timing during early stages of the design. The ever-increasing complexity of system-on-chip design, coupled with uncorrelated tool flows, makes it more difficult to achieve design closure on all fronts. Special tool capabilities are needed to ensure that all aspects of the design, from timing cl osure to signal integrity to power requirements, are addressed simultaneously.

"Signal integrity" refers to a broad set of integrated-circuit design issues, such as crosstalk noise, electromigration and IR drop, and such manufacturing-related issues as antenna effects. Variations on a single die complicate the design process. For a successful tapeout and reliability, signal integrity issues must be resolved during the design flow.

The ability of a physical design system concurrently to analyze and correct for various signal integrity problems during a physical implementation flow is highly dependent on the architecture of the design system. A single data model, combined with an integrated design system, is necessary to address deep-submicron effects efficiently and to provide design closure in a timely manner.

With the scaling of the horizontal dimensions of wires, the aspect ratio of the horizontal to vertical dimensions is reduced, resulting in increased ratios of coupling capacitan ce (lateral) to ground capacitance (over or under crossovers or to substrate). Depending on the relative rate of switching (rise and fall times of the signals) and the amount of mutual capacitance, there can be significant crosstalk noise. Crosstalk noise, depending on its amplitude and when it happens, can cause false switching or delay uncertainty on the victim net.

Deep-submicron designs often contain millions of devices and run at speeds of hundreds of MHz. The current densities (current per cross-sectional area) in the power and signal lines are consequently high and can result in either power or signal electromigration problems. The electron "wind" induced by the current in the metal power lines causes metal ions to migrate. That phenomenon of transport of mass in the path of a dc flow, as in the metal power lines in the design, is termed power electromigration. The power electromigration effect is harmful from the point of view of design reliability, since the transport of mass can cause open circuits, or shorts, to neighboring wires.

Unified data model needed

IR drop is a signal integrity effect caused by wire resistance and current drawn from the power and ground grids. If the wire resistance is too great or the cell current is higher than predicted, an unacceptable voltage drop may occur. The voltage drop causes the voltage supplied to the affected cells to be lower than required, leading to larger gate and signal delays, which in turn can cause timing degradation in the signal paths as well as clock skew. Voltage drop on power and ground grids also reduces the noise margins and compromises the signal integrity of the design.

Antenna and metal fill are two of the manufacturing concerns that must be addressed during physical design. Antenna problems occur during the manufacturing of chips. During the metallization steps, some wires connected to the polysilicon gates of transistors in the design could "float" and collect charge because of the ion-etching process. V oltages on those wires can exceed polysilicon gate breakdown voltages, thereby damaging the chip. Metal fill is required to maintain a uniform metal density across the chip on each layer and thereby ensure planarity during the chemical-mechanical polishing process.

In most conventional IC design flows, signal integrity analysis is performed as a post-layout activity. Attempting to analyze and correct for these issues post-layout often results in costly and time-consuming design iterations, failed schedules, reduced product performance and even larger die sizes with poorer manufacturing yield. A single data model and an integrated design system are necessary to improve productivity and ensure predictable design closure.

To enable repair post-layout, conventional IC design flows build pessimism throughout the design process. The pessimism compensates for uncorrelated tools that are used in the flow. The more uncorrelated point tools used in a design flow, the more pessimism there must be in ord er to prevent costly iterations. Many designs fail to close not because of signal integrity effects but because of the pessimism built into the design flow.

In nanometer technologies, signal integrity must be addressed as an integral part of the design flow. It would be too late to wait until after detailed routing to correct for electromigration, or crosstalk. During placement, the design must be well-tuned, with comparable slews, drivers matched to loads and no long resistive wires. Extraction and wire model estimators must be aware of metal filling that will be applied as postprocessing. IR drop analysis done postlayout may give accurate results, but fixes are limited in cases where the addition of new stripes or larger vias may not be possible.

The design flow should be based on the same data model from start to end to address nanometer-design challenges. Using a single, unified data model, signal integrity fixing or avoidance done at early stages can be retained throughout the remainder of the flow as more fixes and avoidances are performed.

For example, most signal electromigration problems can be corrected early in the design flow once global routes are available. Throughout the remainder of the flow, wire widths and layer assignments can be maintained, and new violations that may be discovered can be fixed incrementally.

Similarly, IR drop analysis with early placement results can drive optimization in the remainder of the flow in terms of voltage-dependent cell delays. For example, input-to-output logic cell delays are affected by power and ground voltage-drop effects, which are not accounted for in traditional timing analysis.

But the relationship between voltage drop and delay is nonlinear, and it it thus impossible to guardband against this effect without giving away too much performance. Similarly, voltage-drop effects increase the susceptibility of a victim net to crosstalk-ind uced timing and noise effects.

Crosstalk delay avoidance and repair should be done as early as possible in the design flow. Shortening critical paths and balancing skew across the design during physical synthesis help reduce crosstalk delay problems. Once clock networks are synthesized, hold fixing and setup optimization with crosstalk delay can be performed. Optimization should consider on-chip variation, crosstalk effects, power, voltage drop and other signal integrity effects.

Crosstalk delay repair, combined with on-chip variation, presents a daunting task. Special attention must be paid to avoid overpessimism.

On-chip variation analysis is performed using a two-corner analysis capability of a static timer. During hold checks, the launching clock and data paths are set to be in fast corners, and the reference clock path is set to be in a slow corner. With crosstalk present, the speedup is achieved a ssuming aggressors are switching in the same direction as the victim (friendly switching). For the slow paths, aggressors are assumed to be switching in the opposite direction of the victim (unfriendly switching). Common portions of the clock path cannot simultaneously be at fast and slow corners.

During timing analysis, pessimism due to common portions of the clock tree is removed. Path-based analysis is used to find common points in the clock tree. The difference between fast corner delay and slow corner delay to the common point is calculated as common point pessimism and is added to the slack. Once the slack is corrected, if corrected slack through the new path is worse than the original, the analysis is rerun on a different path to the same timing end point. The process is repeated until there is no other path with slack that is less than the smallest uncorrected slack.

Pessimism removal using a path-based analysis is suitable for reporting, but during optimization this method is very ru n-time-intensive and thus is impractical. A margin-based approach is recommended for optimization. During optimization, the margins are used to account for on-chip variation and crosstalk delay effects. The incremental timing updates during optimization can then be done without considering crosstalk delay or on-chip variation. The added benefit is that the worst corner can be used for setup checking during hold fixing.

The margins are calculated first as a set of slacks at timing end points obtained with crosstalk and on-chip variation turned on. Common-path pessimism is removed in this set of slacks. Then, crosstalk and on-chip variation are turned off, and a new set of slacks is obtained. The difference between the two slacks is stored as margins.

At 0.13 micron and below, it becomes impractical to address signal integrity issues postlayout. Guardbanding, or building pessimism into the design flow via the use of uncorrelated tools, over-constrains nanometer designs and makes it impossible t o achieve design closure. Signal integrity issues must be concurrently analyzed and addressed throughout the design process.

The ability of a physical design system to analyze concurrently and correct various signal integrity problems during physical implementation flow is highly dependent on the architecture of the design system. An integrated design system will improve productivity, while a single, unified data model is necessary to address various deep-submicron effects efficiently.

Emre Tuncer is the director of product development in signal integrity flow at Magma Design Automation (Cupertino, Calif.). He can be reached at emre@magma-da.com.

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