How to improve ROI in SoC designs

How to improve ROI in SoC designs
By Chris Rowen, EE Times
December 15, 2003 (1:19 p.m. EST)
URL: http://www.eetimes.com/story/OEG20031215S0064

Semiconductor fabs can build hundred-million-transistor chips. The community of chip designers knows how to design complex systems-on-chip (SoCs). But can they design these chips at a reasonable cost? Can they design with short enough time-to-market to catch each market wave? Can they get sufficient volume? In short, can they get acceptable return on investment (ROI) in these complex designs?

As the designer integrates more of the electronics of a system-say a digital camera-onto one chip, the SoC naturally becomes more narrowly specialized to the features and price targets of that particular camera. As the number of digital camera models proliferates, perhaps a new SoC is required for each new model. But now that SoC designs cost over $10 million, including mask costs, the chip designer cannot recover the design cost of any but the highest-volume systems. Furthermore, SoC design is slow and risky: Two years from product concept to manufacturing ramp means there's plenty of time for end-market standards to change, the marketing group to change strategy or the engineering team to make mistakes.

Clearly, building a new SoC for every new electronic product sometimes makes for good technical solutions but lousy economics. Economics dictates that each SoC must be designed for a range of products, and this means some important changes in the way that chips are designed.

For one SoC to serve several products, it will become increasingly important that all key functions be programmable-that all hardware features of the chip, especially signal, media, network and security data paths, be reused and adapted dynamically to meet different product needs. The old model of an SoC with a control processor supplemented by blocks of hard register-transfer-level logic just won't give companies the flexibility to share that design among various products.

Thankfully, some relatively new technology can replace hard RTL logic blocks with flexibilit y and programmability, comparable speed and a much shorter design cycle. This new technology automates the creation of highly customized configurable processors that can replace RTL blocks in a fraction of the design time. Because these processors can be exactly configured to application requirements, including optimized instruction sets, memories and interfaces, performance levels skyrocket above standard embedded processors, rivaling RTL hand coding.

Already, many companies are designing highly flexible SoCs with multiple configurable processors. On average, they are using more than five processors per chip, and at the upper end are using more than one hundred processors per chip. These users say that more flexibility is the primary driver for the widening role of processors as building blocks.

In a decision to design a chip, the relevant return on investment is about the volume of chips, margin per chip and cost of design. Using configurable processors affects each factor in that equation. A more programmable chip means more volume, because more related systems can share one common design. Programmability means higher margin, because new capabilities can be quickly added in software, which adds little to chip area or cost. Automatic design of the individual configurable processor blocks and easier integration of all the subsystems into a complete SoC translates into less design time, smaller design teams and lower risk of redesign, since software can fix a much larger fraction of critical bugs. Together, these drive the ROI for chip design in the right direction.

Chris Rowen is president and chief executive officer of Tensilica Inc. (Santa Clara, Calif.).

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