Speedy A/Ds demand stable clocks

Analog-to-digital converters capable of digitizing high-frequency inputs are now available at 14-bit resolution and greater than 100-MHz clock rates. Some of these converters deliver a 75-dB signal-to-noise ratio (SNR) for analog input frequencies in the 20-MHz range, and 72 dB for frequencies up to 200 MHz.

Realizing such high performance in a system, however, incurs costs beyond that of the A/D itself. Specifically, the delivery of a clean, very low-jitter clock is essential to maintain excellent SNR.

Unfortunately, current low-jitter clock technology can be costly when subpicosecond jitter is needed. To establish just how good a reference clock is required to meet the SNR target, the factors affecting converter output accuracy must be established and understood.

Clock technology capable of the necessary performance uses discrete components, thus significantly raising the cost of achieving subpicosecond jitter. Understanding the factors that affect converter accuracy will establish just how good a reference clock must be.

When comparing high-speed A/Ds, digging beyond the number of output bits and the conversion speed is important. A device may be referred to as a 14-bit, 105-Msample/second A/D, but the measurement may not be accurate to a full 14 bits when running at high speeds. High SNR is vital, as any undesired variation (noise, for example) on the input signal voltage will appear as an output error. These error terms can be broken down into subcomponents, such as thermal noise, quantization noise, distortion and jitter.

SNR can be translated to a value found in many data sheets called "effective number of bits," or ENOB. This value is derived by taking the SNR and adding distortion, Sinad (signal-plus-noise-plus-distortion to noise-plus-distortion ratio). ENOB represents the number of output bits that can be relied on to be accurate. It can be expressed in terms of SNR, as shown in this simplified formula:

ENOB = (SNR - 1.76 dB)/6.02

The SNR of data converters consistently continues to improve. State-of-the-art 14-bit converters currently provide 75-dB SNR at speeds approaching 105 Msamples/s and at higher input frequencies. This translates to greater than 12-bit accuracy. As input frequencies continue to rise, the dependence on a clean signal becomes more and more critical. In most state-of-the-art applications where very fast clock rates and high input frequencies are used, the A/D tends to limit the system performance. This invokes the old adage "garbage in/ garbage out," meaning the cleaner the input and clocking network is, the better the A/D performs.

The variation arising from noise on the sampling edge of the clock translates into an error voltage, or uncertainty as to where the sample point falls, and thus reduces the accuracy of the encoded output. The output from the A/D can be no more accurate than either its inherent SNR or the accuracy enabled by the purity of the clock.

These two factors are not directly additive, but each contributes to the total ENOB measure achieved within a system. To extract the maximum performance out of an A/D, a clock must be provided that has edge variation (jitter) low enough to impact the accuracy of the output less than the SNR does. If the clocking signal is clean enough so that the SNR limitations dwarf the jitter impact, the system will achieve the best performance possible from the data converter being used.

The equation relating SNR to jitter is given as:

Where f is the frequency of the clock, and tjitter is the rms jitter of the clock.

The figure on page 61 was generated using this equation. The red lines on the chart indicate the approximate limits of present technology in terms of jitter performance. Inexpensive (sub-$4) clock chips incorporating a complete phase-locked loop (PLL) with on-chip ring oscillator can achieve rms jitter down to about 10 ps. Unfortunately, this technology will not support converters with resolutions higher than 7 ENOB at input frequencies of 100 MHz and higher.

For higher performance, a PLL with an external VCO is required, but the cost of these solutions can easily run to more than half the cost of the converter itself. Further, in order to get above 12 ENOB from a 14-bit A/D at 100 MHz, a designer must upgrade to a good voltage-controlled crystal oscillator (VCXO) combined with a PLL, a solution which will generally cost more than the converter. Converter manufacturers are already working on designs that push the maximum performance capabilities beyond the level where even PLLs with an accompanying VCXO can provide a clean-enough signal. These require dedicated low-noise oscillators, whose costs at these frequencies are very high (hundreds of dollars).

Clearly, an opportunity exists for a more cost-effective clocking solution to support the newest, most-advanced high-speed converters. Whether that solution proves to be a cost breakthrough in dedicated oscillators, a performance breakthrough in PLL technology or some new signal synthesis technique is not yet clear.

Converter users are clamoring for a solution to this growing problem, and are looking to converter manufacturers for guidance. Fortunately, initiatives are in progress that include exploring both PLL technological improvements and new digital synthesis techniques; watch for new clock products that support subpicosecond jitter performance. This will help push the cost of clocking tomorrow's high-performance, high-speed converters to more reasonable levels and reduce the risk of system-related jitter components affecting the performance of these converters.

Jeff Keip (jeff.keip@analog.com) is senior product-marketing manager at the Clocks and Signal Synthesis Products Division of Analog Devices Inc. (Greensboro, N.C.).